Frequently Asked Questions And Answers: Part 3
This is a monthly posting to comp.lang.vhdl containing information products and services for VHDL (commercial and public domain) Please send additional information directly to the editor:
edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska) You can also use this form to drop me a short note if your client can handle FORMs.Corrections and suggestions are appreciated. Thanks for all corrections.
There are three other regular postings: part 1 lists general information on VHDL, part 2 lists books on VHDL, part 4 contains descriptions for a number of terms and phrases used to define VHDL.
This product list is never up to date it seems - please help to update it. This list is without any guarantee to be complete or correct. It is included to enable contacts to vendors. It does not contain version, quality or price information. (Please accept, that actually this information changes to fast -too much work to keep such information up to date, but if there is a volunteer willing to take this part...:-). If some kind of judgment is included ('specialist' for example) it's not my personal opinion but a remark from the vendor himself.
Contact: Peter Reintjes, email: pbr@quintus.com
A revised Version can now be found at
Contact: Krishnaprasad Thirunarayan (Prasad),
email: tkprasad@cs.wright.edu, phone: (513)-873-5109
URL: ftp://ftp.cs.wright.edu/pub/vhdl/
Files: VHDL93_SWI_2.7.14.tar.gz and README_SWI_2.7.14
Contact: Krishnaprasad Thirunarayan (Prasad),
email: tkprasad@cs.wright.edu, phone: (513)-873-5109
URL: http://www.cs.wright.edu/people/faculty/tkprasad
URL: http://www-nt.e-technik.uni-dortmund.de/m_mvo/vaul.html
The tools are available from
Contact: email: sprudel@c-lab.de
URL: http://www.c-lab.de/~sprudel/vhdl-parser/
Contact: email: grimm@ti.informatik.uni-frankfurt.de
URL: http://www.ti.informatik.uni-frankfurt.de/grimm/hybrid.html
URL: http://poppy.snu.ac.kr/vdt-ivsim/vhdlsim.html
URL: ftp://poppy.snu.ac.kr/pub/vhdl/
URL: http://www-asim.lip6.fr/alliance/index.gb.html
URL: ftp://cao-vlsi.ibp.fr/pub/alliance/
URL: ftp://ftp.ibp.fr/ibp/softs/masi/alliance/
The following packages add support for VHDL editing to GNU Emacs or XEmacs:
URL: http://www.geocities.com/SiliconValley/Peaks/8287/
For older version of vhdl-mode see ftp://ftp.eda.com.au/pub/emacs/.
URL: http://www.vim.org/
URL: ftp://ftp.informatik.uni-stuttgart.de/pub/vhdl/mvp_v11
An updated version of MVP v1.1.1 (updated for USA A size paper and
assoaciated font bugs) is also available at
URL: http://vhdl.org/vi/vhdlsynth/mvp_v1_1_1.tar.gz
URL: ftp://vhdl.org/pub/vhdlsynth/mvp_v1_1_1.tar.gz
Contact: Michael Knieser, email: knieser@alpha.ces.cwru.edu
There are differnt version for VHDL 1076/87 and VHDL 1076/93 available
Contact: Professor J. R. Armstrong, Bradley Department of
Electrical Engineering, Virginia Tech, Blacksburg, VA. 24061-0111,
phone: (540) 231-4723, fax: (540) 231-3362, email: jra@vt.edu
URL: ftp://digres3.visc.vt.edu/pub/suite/vpi.tar
See also FAQ Part 1, Section 4.4.
Contact: Jon Connell:jco@egnetz.uebemc.siemens.de
URL: http://bear.ces.cwru.edu/tools.html
URL: ftp://alpha.ces.cwru.edu/pub/VHDL/contrib/vhdl2html.tar.gz
Contribution are welcommed in /incoming (management by
herve@erm1.u-strasbg.fr) Suggestions and encouragments at
herve@erm1.u-strasbg.fr.
The database structure and contents are:
Contact: email: herve@erm1.u-strasbg.fr
URL: ftp://erm1.u-strasbg.fr/pub/vhdl/
URL: http://erm1.u-strasbg.fr/db/
Contact: Eric Anthony Jones, email: EricAJones@aol.com
URL: http://lister.cms.livjm.ac.uk/homepage/student/cmsejone/index.html
Contact: Cristian Ghezzi, email: xtian@sna.co.umist.ac.uk
URL: http://www.co.umist.ac.uk/~xtian/v2c/v2c.html
Contact: email: A.C.Verschueren@ele.tue.nl
URL: http://www.eb.ele.tue.nl/proj/idassfly.html
FMF provides:
Contact: email: rick.munden@vhdl.org
URL: http://vhdl.org/fmf
2. Companies and their Products/Services
******************************************************************** Accolade Design Automation, Inc. 550 Kirkland Way, Suite 200 Kirkland, WA 98033 USA (425) 828-2122, (800) 470-2686 (425) 739-2163 FAX http://www.acc-eda.com email: info@acc-eda.com WWW: http://www.acc-eda.com Japan Distributor: InterLink, Inc. 1-5-21-1325 Mori Isogo-Ku Yokohama 235 JAPAN Phone: 81-45-40-28220 Accolade Design Automation, Inc. develops and markets high-performance tools for VHDL and FPGA users. Products include a Microsoft Windows (3.1, `95 and NT compatible) VHDL simulator in Personal and Professional editions. The PeakVHDL simulator uses direct-compile technology, and includes a source code browser, integrated 'make' facilities, and integrated source file editor. The PeakFPGA synthesis product integrates directly with PeakVHDL to provide a combined simulation and synthesis environment for popular FPGA devices including Xilinx, Altera, Actel, Lattice, Lucent and AMD. The Accolade Design Automation Web Site http://www.acc-eda.com includes a free Introduction to VHDL tutorial. Evaluation software is available, as is a textbook titled "VHDL Made Easy!". Call or email for special low-cost educational programs and packages. ******************************************************************** Alternative System Concepts, Inc. PO Box 128 Windham NH 03087 tel (603) 437-2234 fax (603) 437-ASC2 email: info@ascinc.com www: http://www.ascinc.com verilog2vhdl : verilog2vhdl translates hierarchical Verilog HDL to VHDL by using an HDL object kernel. It makes a full translation of structural Verilog, and a partial translation of behavioral Verilog. It supports a subset of Verilog and uses a combination of IEEE and tool-specific VHDL packages to perform the translation. VHDL that is created by verilog2vhdl is functionally equivalent to input Verilog, and because of one-to-one mapping of Verilog to VHDL, output VHDL is easy to understand. Output VHDL is IEEE 1076-1993 compliant. VHDL2verilog: VHDL2verilog translates hierarchical VHDL (full structural, part RTL) to Verilog HDL. Verilog that is created by VHDL2verilog is functionally equivalent to input VHDL. Both IEEE Std 1076-1993 or IEEE Std 1076-1987 compliant VHDLs are processed by the system and output Verilog is compatible with any Verilog-XL compatible simulator. AVAILABLE June '1995 FRITS: FRITS is an object-oriented framework for EDA tool development. FRITS translates Verilog HDL or VHDL descriptions into a common object format and stores the data in an object kernel in memory. The object kernel is accessible to the EDA tool developer via an Application Program Interface (API). FRITS also provides an elegant mechanism for easy extraction of the stored design data. If not mentioned, ALL TOOLS ARE AVAILABLE NOW FOR SunOS 4.1.x. Please send requests for other platforms to 'info@ascinc.com'. ******************************************************************** Ascent Technology, Inc. Readers Note: name changed; now VLT 2075 North Capitol Avenue, Suite C San Jose, CA 95132 phone: (408) 945-6635, fax: (408) 946-0922 contact: Rindert Schutten MetaView : basic design environment to be customized VHDL/DA : Design Assistant (VHDL/DA) : MetaView based environment for design management, structure editing, browsing, state machine editing, architecture editing source code transformation ( for synthesis ) ********************************************************************** Associated Professional Systems (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA Phone: 410-515-3883 Fax: 410-661-2760 email: eda@associatedpro.com APS develops FPGA test boards and packages them with EDA software at very low prices. The APS-X84 XILINX Foundation Kits offer VHDL Schematic capture, simulator, ABEL HDL, XACT router, and VHDL multimedia tutorial plus the X84 ISA FPGA test utility board for prices as low as $650.00. The kit comes with VHDL examples and C code to control and download to the FPGA board from either the supplied XCHECKER cable or from the PC ISA bus. Check out the details at http://www.associatedpro.com/. These deals can't be beat! ******************************************************************** CAD Language Systems, Inc.- assimilated from Compass Design Automation, Inc. Compass Design Automation, Inc. Suite 101, 5457 Twin Knolls Road Columbia, MD 21045 USA old adresses (at least email should still work) USA: 5457 Twin Knolls Road, Suite 101 Columbia, MD 21045 Phone: (410) 992-5700 Fax: (410) 992-3536 Email: support@clsi.COM Japan: Shunsuke Miyakushi Bussan Electronic Systems Technology, Inc. Sanseido Building 4-15-3 Nishi-Shin-Juku Shin Juku-Ku, Tokyo /60, Japan Phone: +81 3 3374 1161 Fax: +81 3 3374 9450 Europe: (Please contact USA) Products: VTIP - VHDL Tool Integration Platform: this is a VHDL analyzer, a VHDL generator, and an intermediate form database with a procedural interface. Full 1076-1987. RVCG - Retargetable VHDL Code Generator: generates C code for use in VHDL simulation using the VTIP. Allows integration of VHDL simulation with existing (or new) simulators. VMT - VHDL Modelling Tool: a compiled code simulation system based on the RVCG, high-performance kernel, and Motif interface. VFormal - Formally verifies the equivalence or non-equivalence of VHDL designs with respect to their specifications. A program for training, university&research program ******************************************************************** Cadence Design Systems, Inc. HDL Design Group 270 Billerica Road Chelmsford MA 01824 508-667-8811 OR 555 River Oaks Pkwy. San Jose, Calif. 951134 Eileen Elam (Public relations representative) (408) 943-1234 Germany: Mr. Grothe phone: 02236 68051 seems now: 02236/962130 (Vertrieb) Leapfrog - Full IEEE 1076 Simulation Environment Using Native Compiled Code Synergy - VHDL and Verilog Logic Synthesis and Optimization Verilog-XL - Verilog HDL and accelerated gate simulator Valid (part of CADENCE now) 2820 Orchard Pkwy. San Jose, Calif. 95134 Germany: Muenchen, phone: 089/710050 seems now: 089/570960 (Applikation) compiler, simulator Now sells Intermetrics tools www: http://www.cadence.com/ ******************************************************************** Cascade Design Automation 3650 131st Av. SE #650 Bellevue WA 98006 (206) 643-0200 EPOCH/VHDL -- Physical design tools which accept VHDL input and generate VHDL gate-level output with accurate timing. Includes a library of models for standard-cells and parameterized components such as memories and datapath elements. Also accepts input from Verilog and several schematic entry platforms. Gate-level VHDL output can be generated regardless of where the input came from. Allows VHDL to be mixed with schematics or Verilog. A Synopsys Design Compiler interface is also available. www: http://www.cdac.com/ ******************************************************************** Computer General Electronic Design Ltd. Readers comment: ceased trading in August 1992 (I used to work for them). Contact: Arthur Burnley, Sales Manager Computer General Electronic Design Ltd 5 Greenways Business Park Bellinger Close Chippenham Wiltshire SN15 1BN U.K. phone:+44 249 445566 Fax:+44 249 445595 e-mail:arthur@cged.co.uk Specialists in VHDL design, synthesis, simulation and test. Products/services include: - VHDL Design Station. Design capture, synthesis, simulation workstation including: ECS Schematic capture, LOCAM synthesis, CLSI VHDL Modelling kit. Basic configuration inc. SparcStation costs UK L19,950. - CLSI's VHDL Modelling Kit (distributor), low cost, interactive, VHDL compiler and simulator - LOCAM including VSyn, fast, memory efficient synthesis for structural, dataflow and behavioral VHDL - OPTIMA, retiming synthesis tool, which adds/removes pipelining and dramatically improves the results of logic synthesis for area, timing and power - Panther Test synthesis which may be integrated in synthesis flow from VHDL - The ELLA HDL/ASIC design environment / behavioural simulator - ELLA -> VHDL translator - VHDL and ASIC Design Services ******************************************************************** Cypress Semiconductor Contact: Cypress Semiconductor Corporation 3901 N. First St. San Jose, California 95134, U.S.A Phone: (408) 943-2600 Fax : (408) 943-2741 - Information is also available from any of our sales offices Worldwide - Warp2: Warp2 is a state-of-the-art VHDL compiler for designing with Cypress PROMs and PLDs. Warp2 utilizes a proper subset of IEEE 1076 VHDL as its Hardware Description Language (HDL) for its design entry. Warp2 accepts VHDL input, synthesizes and optimizes the entered design, and outputs an industry standard JEDEC map for the desired device. This JEDEC file may then be simulated with the Cypress NOVA simulator (included in Warp2). Warp2 is available on PC(Windows) and Sun platforms. www: http://www.cypress.com/ ******************************************************************** Data I/O Corporation 10525 Willows Road NE P.O. Box 97046 Redmond, WA 98073-9746 USA (206) 881-6444 Synario(TM) Design Software is a fully integrated solution combining Synario ECS Schematic Entry, and ABEL(TM) or VHDL Design Entry; with fast functional and timing Verilog simulation, or the popular Model Technology V-System VHDL Simulator. Synario is the most advanced, productive, and tightly integrated best-of-class Windows(TM) EDA design tool. You can enter and simulate designs by combining multiple forms of entry into a single design while using vendor fitting and place-and-route software. www: http://www.data-io.com/ ******************************************************************** DS Diagonal Systems Inc. 800 El Camino Real West Suite 180 Mountain View, CA 94040 Phone (415) 903 2255 Fax (415) 903 2237 DS Diagonal Systems AG Tumigerstr. 71 CH-8606 Greifensee Switzerland Phone +41 1 905 60 60 Fax +41 1 905 60 69 WWW: http://www.diagonal.com/ E-mail (from all countries): info@diagonal.ch Products: WAVE-Link is a highly interactive, graphical toolset for generating digital stimulus waveforms and defining expected responses that are simulator and ATE system independent. Stimulus creation is fast and and visual - free from the specific syntax of any simulator or ATE system. WAVE-Link is your common front-end tool for VHDL, Verilog and gate level simulators. CHECK-Link: design verification according to company's guidelines; testability verified during design. CAT-Link: design and layout consistency verification; design and layout data transfer to manufacturing (ATE & Pick/Place) ******************************************************************** EASICS, the VHDL Design Company. Easics is an independent ASIC design company and offers a variety of services related to the design of digital ASICs. These services include the design of ASICs (up to a testable netlist) and FPGAs (including prototyping), VHDL-based design consulting and ASIC design feasibility studies. Easics has a track record of ASIC designs in telecommunications (ATM, SONET, SDH), bus interfaces and Digital Signal Processing applications. For more information, look at our WWW-site http://www.easics.com/ or contact Dirk Callaerts, Marketing Manager (mailto:dirk@easics.be), Interleuvenlaan 86, B-3001 Leuven, BELGIUM Tel +32-16-395 604, Fax +32-16-395 619 ******************************************************************** Exemplar Logic, Inc. Exemplar Logic's Galileo tool suite is a complete High-Level Design environment for the synthesis, simulation and timing verification of FPGA, CPLD and ASIC designs. Exemplar Logic supports both VHDL and Verilog HDL at the Register Transfer Level (RTL), dataflow level, and at the netlist level. Support of HDL constructs is at the leading-edge in the industry and assures design entry at the highest level of abstraction. Exemplar Logic provides a truly VITAL based design flow with VITAL libraries for accelerated simulation. Visit the Exemplar Logic WEB site (http://www.exemplar.com) for more information or contact: Shubha Shukla Exemplar Logic, Inc. Product Marketing Engineer 815 Atlantic Avenue, Ste.105 E-mail: shukla@exemplar.com Alameda, CA 94501-2274 Direct: 510-337-3741 USA Fax: 510-337-3799 510-337-3700 ******************************************************************** FTL Systems, Inc. Contact: 924 Sierra Lane NE Rochester, MN 55906 products@ftlsys.com Main Number: +1 507 288 3154 Web: http://www.ftlsystems.com Distributors available in North America and Japan (see WWW for details) Products: VHDL Complete OEM Analyzer/Elaborator (Fall 1996 Release) VHDL Optimizing Compiler/Simulator (Early 1997 Release) Other VHDL and Verilog products coming soon... Public Service: VHDL-93, VHDL-AMS Validation Suite (1997 Release) Glad to meet you at: EuroDAC US DAC ASP DAC VIUF/IVC ******************************************************************** GenRad Ltd. Design Automation Products Waterside Gardens Fareham, HANTS PO16 8RR G.B.-England www: http://www.genrad.com/ ******************************************************************** Green Mountain Computing Systems 2 Joseph Lane Essex Junction, VT 05452 email: thibault@together.net Green Mountain VHDL compiler designed for educational use but there are no special requirements for purchase, DOS, generates native 80386 machine code, includes: On-line manual that describes the operation of the compiler as well as GM VHDL. GM VHDL compiler/linker for DOS (supports most of the IEEE std 1076-1987) Two simulation environments for batch and interactive simulation with waveform display. Precompiled packages standard,textio,std_logic_1164. Free technical support (via e-mail) and free minor releases updates. Evaluation Version is available from the WWW site. www: http://together.net/~thibault/home.htm ******************************************************************** i LOGIX 22 Third Av. Burlington, MA 01803 Tel. 617 272-8090 Fax. 617 272-8035 EXPRESSV-HDL, a graphical behavioral modeling tool allows hardware engineers to design with the precise graphical language of STATECHARTS- a powerful extension of state transition diagrams. Designers can create behavioral and functional models of circuits, analyze the design using the simulation and dynamic analysis capabilities proving that the design is correct before code generation. EXPRESSV-HDL then automatically generates VHDL and VERILOG from the models both of which are fully compatible with industry leading HDL simulation and synthesis tools. www: http://www.ilogix.com/ ******************************************************************** interHDL, Inc. 4984 El Camino Real Suite 210 Los Altos, CA 94022-1433 USA Tel: 415 428 4200 Fax: 415 428 4201 email: info@interhdl.com ftp site: http://ftp.interhdl.com web page: http://www.interhdl.com V to VH: Verilog to VHDL translator. Converts Verilog designs into equivalent VHDL designs. Covers about 95% of the language including the full structural and synthesizable subsets. The output VHDL code is semantically and synthesis-wise equivalent to Verilog source, and is very readable. V to VL: VHDL to Verilog translator. Converts VHDL designs into equivalent Verilog designs. Covers about 95% of the language including the full structural and synthesizable subsets. The output Verilog code is semantically and synthesis-wise equivalent to VHDL source, and is very readable. Translation include generate statements, enumerations, aggregate constants, etc. Comments are being preserved in the output code. ******************************************************************** Intermetrics Phone: (703) 827-2606 FAX: (703) 827-2609 Addr: 7918 Jones Branch Drive, Suite 710 McLean, VA 22102 VHDL Design Environment simulation system SUN/DEC University Program Readers note: no longer has any commercial VHDL tools for sale ******************************************************************** I.S.T (Innovative Synthesis Technologies) France: office adress: 4, place Robert-Schuman, EUROPOLE, 38000 Grenoble-FRANCE contact: Pierre Abouzeid Phone# (33) 76 70 51 00 Fax# (33) 76 84 12 61 E-mail: Pierre@atarax.imag.fr USA: P.O. Box 1897, Danville, CA 94526-1897 , USA. contact: Peter E. Robinson Phone# 510-736-2302 Fax# 510-736-6199 Voice Mail# 510-275-2752 Products: ASYL+ is a commercial synthesis tool which offers the following features: SYNTHESIS: From HDL specifications including PALASM, open ABEL and VHDL using target dedicated synthesis techniques. Supported technologies include FPGAs/CPLDs (Xilinx, Actel, Quicklogic, AT&T, Cypress, Altera and AMD) and ASIC technologies (Nec, Fujitsu, Hitachi, VLSI, SGS-Thomson, ES2). ASYL+ VHDL solution offers macroblock selection including parameterized generators. Macroblock libraries from XILINX (XBLOX), ACTEL, ALTERA, AT&T, VLSI technology are supported. An efficient FPGA package partitionner is available for ACTEL and XILINX technologies. OPTIMIZATION:Netlists optimization for all technologies described above. Area, speed, or trade-off oriented optimizations taking into account specific user constraints are available. Recent innovative techniques (direct mapping on binary decision diagram representation, wiring preparation) allow efficient results: reduced memory space requirements and running times. MIGRATION:The ASYL+ migration enables designs targeted to virtually any ASIC or FPGA/CPLD technology to be migrated and mapped fully automatically to any other supported devices. Effective macroblock migration with efficient optimization. The following targets are under development: Lattice, Motorola, Atmel and new ASIC libraries (Toshiba, AMS, ...) Supported platforms: SUN SPARC, HP 9000, PC 386/486. ASYL+ has been selected by the EEC for teaching in the European EUROCHIP project and about 200 licences are running in european universities. ******************************************************************** ITD Institute for Technology Development Advanced MicroElectronics Division Office Adress: 1080 River Oaks Drive Suite A-250 Jackson, MS 39208 contact: Dan Johnson (VHDL modeling group manager) phone: (601) 932-7620, fax: (601) 932-7621 email: danj@aue.com or design@aue.com Post Office Box Address: Advanced Microelectronics P.O. Box 55729 Jackson, MS 39296-5729 Corporate Office Phone Number: (601) 960-3600 Note: Use the corporate office phone to leave messages if the phones have not been connected at River Oaks. VHDL STANDARD COMPONENT LIBRARY Version 2.1 AuE has completed a new release of its VHDL Standard Component Library. The previous version 1.1, was released in July 1990. All models are fully compliant to the EIA Commercial Component Model Specifications (EIA-567) and the VHDL Data Item Description (DI-EGDS-80811). All models include a testbench compliant to the Waveform and Vector Exchange Specifications (WAVES PAR 1029.1/D1). Timing modules characterized to manufacturers' data sheets are included in each model. Timing parameters are dependent on voltage, temperature and capacitive loading. A Software License Agreement must be signed and returned before the library can be shipped. AuE's VHDL V2.1 Library may be obtained via FTP or cartridge tape. Library distributions via FTP are in compressed tar format and include all documentation. Distributions via FTP have a distribution fee of $150, paid in advance. Distributions shipped on cartridge tape are in tar format. Documentation is shipped with the tape. DISTRIBUTION CHARGE: $150 for VHDL V2.1 Library, plus $150 administrative fee. International shipments are made by Federal Express, if available, and all duties and taxes ( if applicable) are the responsibility of the licensee. To obtain ordering information via the Internet, the address is: model@aue.com also provides contract VHDL modeling services ******************************************************************** JCR Research Laboratories Inc. contact: Erwin Warshawsky phone: (714) 974-2201 email at erwin@jrs.com. C to VHDL and ADA to VHDL translator ******************************************************************** LEDA SA (Languages for Design Automation) 35 Avenue du Granier 38240 MEYLAN - FRANCE contact: Francis Sourbier phone: +33-76 41 92 43, fax: +33-76 41 92 44 e-mail: support@leda.fr http://worldserver.oleane.com LEDA is a French company providing training, consulting, modeling and development services. o LEDA VHDL System family of products (VHDL Front-End Toolbox) contains: - A Full-IEEE VHDL'93 Analyzer performing all syntactic and semantic analysis of VHDL source code and transforming it into a binary representation known as the "VHDL Intermediate Format" (VIF). Includes a Library Manager, a VIF Browser allowing the user to examine a VIF representation, the LPI (LEDA Procedural Interface) used to access and manipulate the VIF data base and Schemagen, allowing the definition of user extendable VIF data bases and associated LPI and browser. A Reverse Analyzer allows the generation of VHDL source code from the VIF representation of a VHDL unit. - GraphGen, a Control Flow and Data Flow Graph (CFG/DFG) generator useful for the development of synthesis tools. - APEX, an Atomic Property EXtractor for synthesis and simulation environments. - GEME, an elaborator allowing the computation of globally static expressions (possibly including generic actual values) with sequential code evaluation capabilities. - VELS, a VHDL synthesis subsets checkers, with transformation capabilities. o LEDA Verilog System (LVeS Verilog front-End) performing all syntactic and semantic analysys of the Verilog source code and transforming it into a binary representation known as the "Verilog Intermediate Format" (VeIF). Includes a Library Manager, a VeIF Browser and a Procedural Interface. o KRYPTON: source model encrypter. Transforms VHDL into VHDL. Allows the generation of a functionally correct model, free of all documentation, synthesis tunings, resource packages, etc. The user can choose to leave part of the model uncrypted, for example the external interface or some internal objects important for simulation trace. o HELIOS: Hierarchical Elaborator of VHDL Generic Models for getting around limitations of VHDL CAD tools. Performs propagation of generic values, execution of configuration specifications, constant propagation, VHDL source code generation etc. o VHDL training and product distribution. A University and research program exists. ******************************************************************** Logic Automation new name: Logic Modelling Corp. Farley Hall London Road Bracknell, Berks RG12 5EU, UNITED KINGDOM phone: +1 503-690-6900, FAX +44 344 863990 library of models, ******************************************************************** LSI Logic Corporation 1551 McCarthy Blvd Milpitas CA 95035 United States Tel: 408.433.8000 FAX: 408.433.8989 Silicon 1076: VHDL development environment, includes the Vantage simulator and the Synopsys logic synthesizer. Also a high level synthesis module called Explorer(scheduling binding and allocation for behavioral code). links to LSI's MDE environment. www: http://www.lsilogic.com/ ******************************************************************** Paul J. Menchini Menchini & Associates email: mench@mench.com P.O. Box 71767 voice: +1 919-479-1670 Durham, NC 27722-1767 pager: +1 800-306-8494 USA fax: +1 919-479-1671 WWW: http://www.mench.com Mr. Menchini is an independent EDA Consultant with over seventeen years of industrial EDA experience, specializing in the hardware description languages VHDL and Verilog, and in high-level design methodologies. He offers training, custom code and model development, and marketing and technology consulting to EDA companies and users. His current and former clients include Chrysalis Symbolic Design, DEC, Ikos, Research Triangle Institute, Rosemount Aerospace, Synopsys, Tellabs, Thinking Machines, TSSI, VHDL International, Viewlogic, and Zycad. Mr. Menchini, who holds Bachelor's and Master's degrees from Stanford University, is a member of IEEE (Senior Member), CS, ACM, IFIP Working Group 10.2, and the Association for Automated Reasoning. ******************************************************************** MCC Microelectronics and Computer Technology Corp. 3500 West Balcones Center Dr. Austin, Texas 78759 USA Phone: +1 (512) 338 3598 e-mail: ask@mcc.com simulator www: http://www.mcc.com/ ******************************************************************** Model Technology Incorporated 8905 S.W. Nimbus Ave, Suite 150 Beaverton, OR. 97008-7100 USA Model Technology is the market leader in VHDL according to Dataquest based on units and revenue. V-System is considered the most popular VHDL simulator with over 11,000 revenue units sold worldwide and is available on Workstation (HP, SUN Solaris, SUNOS5, and RS600) and PC (x86 and Pentium based Windows 3.1, 95, and NT). Model Technology sells a full line of HDL solutions for VHDL, Verilog, and Mixed HDL simulation. V-System is sold direct through Value-Added Resellers and through OEM relationships such as Mentor Graphics, Exemplar, Data-I/O and Escalade. For more product information as well as who to contact: please visit our home page at http://www.model.com, email us at sales@model.com, or call us at 1-503-641-1340 ******************************************************************** Mentor Graphics 8005 S.W. Boeckman Road Wilsonville, Oregon 97070-7777 for System-1076 and QuickVHDL contact: Brian Caslis (brian_caslis@mentorg.com) phone: hone: (503)685-1404 Fax: (503)685-1268 for VHDLsim contact: John Harris (john_harris@mentog.com) phone: 503-685-4735 Germany: Duesseldorf Sales Office phone: 0211/591011 Fully integrated compiler/simulator/debugger design development system: System-1076 - QuickSim-II based VHDL. Source-level debugger, supporting VHDL concurrent events. Integrated in the Concurrent Design(TM) environment - available now. VHDLsim - Explorer Lsim based VHDL. Focused on IC design, VHDLsim is integrated within the GDT design environment, and supports the use of VHDL models with analog and M models in the same design. AutoLogic VHDL - VHDL synthesis VHDLNet - netlist schematics into VHDL structural description Design Architect - VHDL oriented text editor (and schematic editor) QuickVHDL - Full IEEE 1076 Simulation Environment using Direct-Compiled Code Technology. Includes integration with Design Architect for entry and AutoLogic VHDL for synthesis. Available September 1993 ******************************************************************** Papillon Research Corp. - Specialists in Hardware Engineering 52 Domino Dr. Concord, MA 01742 ph: 978-371-9115 fax: 978-371-9175 email: info@papillonres.com www: http://www.papillonres.com/~papillon SERVICES: Full product design including: architecture, ASIC, FPGA, mechanical, and analog design, EMI design toward agency compliance, device modeling, synthesizable modeling - all hardware related services. PRODUCTS: VHDL models: R3051 family, 29030, 79C940, CY7C960 & 964, VME bus, others. The RXI/RXD chipset for the IDTR3051 family of RISC processors provides DRAM/VRAM controller, I/O control, etc. ******************************************************************** Pittsburgh University of [PD/SW?] Prof. Steven Levitan, Dept. of Electrical Engineering 348 Benedum Engineering Hall Univ. of Pitsburgh, 15261 email: vhdl@ee.pitt.edu see anonymous ftp: ee.pitt.edu (130.49.15.1) in pub/vhdl-info for files README, letter.txt, license.PS, assurance.PS ... not public domain, but 150$ analyzer/simulator and sources ******************************************************************** Precedence Incorporated 4675 Stevens Creek Blvd., Suite 250 Santa Clara, CA 95051 USA Tel: (408) 345-4880 Fax: (408) 345-4884 SimMatrix co-simulation products: Mentor Graphics Quicksim II / Cadence Verilog-XL Mentor Graphics Quicksim II / Mentor Graphics Lsim Mentor Graphics Lsim / Zycad XP Cadence Verilog / Vantage Spreadsheet Co-simulation Cadence Verilog / Quickturn hardware emulator Co-simulation Cadence Verilog / EPIC Design TimeMill and PowerMill Co-simulation Cadence Verilog / Mentor Lsim Co-simulation Cadence Verilog / Silvaco SmartSpice Co-simulation Viewlogic Viewsim - VHDL / Cadence Verilog-XL Viewlogic Viewsim - VHDL / Zycad XP Viewlogic Viewsim - VHDL / Silvaco SmartSpice Co-simulation Description:Precedence co-simulation products allow designers to simulate using multiple VHDL and non-VHDL design verification tools as shown above, simultaneously and transparently. This is useful for IC, ASIC and PCB simulation which includes blocks or models in a variety of simulators and/or languages, such as combining VHDL and HDL. At the heart of this integrated simulation environment is Precedence's extensible SimMatrix simulation backplane. Sun, some HP Additional platforms and simulators may be added based on demand. www: http://www.precedence.com/ ******************************************************************** PROXY Modeling 1580 Washington Blvd. Fremont, CA 94539 Tel: (510)-440-VHDL Fax: (510)-440-8852 Products: High level design methodology consulting VHDL modeling Custom training and documentation On-site support Tool integration Development of specialized tools The principals of PROXY Modeling have been involved in the development and support of VHDL based design automation products since the introduction of the language with Vantage Analysis Systems. They have provided consulting, support, and tools for large Department of Defense projects like F22 and RASSP and many of the largest commercial VHDL users. Active involvement in VHDL currently includes teaching 'VHDL Basics' class at The University Of California, Berkeley Extension (since 1991), presenting tutorials in VIUF and IDEA conferences, and participating in committees. PROXY Modeling works with ASIC and FPGA design teams providing on-site support to streamline the design process, developing methodology to manage large projects, and training engineers in the effective use of VHDL with high level design. VHDL tool vendors utilize PROXY to test and benchmark new products. ASIC and FPGA vendors have used PROXY to develop and present training classes and write user documentation. PROXY provides modeling services to create custom parts in VHDL or C. PROXY also builds point tools to improve integration and to enhance the capabilities of the simulator through the C language interface. http://www.proxymod.com/ ******************************************************************** Qualis Design Corpration PO Box 4444 Beaverton, OR, USA, 97075-4444 (503) 531-0377 fax: (503) 629-5525 email: info@qualis.com FTP: ftp://ftp.qualis.com WWW: http://www.qualis.com Overview Qualis Design Corp of Beaverton, OR, offers high quality expert consulting services in all aspects of using HDLs (both VHDL and Verilog) including training, design environment, code management, tooling, tool integration, behavioral modeling, test planning, testbench infrastructure, testcase implementation, synthesis, gate-level verification and more... Training Our classes differ from the traditional bottom-up, gate-to-behavioral HDL training approach and reverses the flow starting with high-level descriptions, testbench and top-down methodology. We feel this high-level approach to training better fits an advanced design process encouraging students to learn a methodology, and not just a language. More than 70% of the time is spent on hands-on exercises using the latest version of state-of-the-art VHDL, Verilog and synthesis systems. High-Level Design Using VHDL (5 days) High-Level Design Using Verilog (5 days) Advanced Techniques Using VHDL (3 days) Advanced Techniques Using Verilog (3 days) Products Anon FTP VHDL language Quick Reference Card pub/qrcs 1164-based packages Quick Reference Card pub/qrcs Verilog language Quick Reference Card pub/qrcs Makefile generator for VHDL models pub/vhdl/vmk ******************************************************************** Ravi Technologies, Inc. 3080 Olcott St., Suite 220C Santa Clara, CA 95054 ph: (408) 748-7400 fx: (408) 748-7402 email: savel%ravitech@uunet.uu.net provides full VHDL services: Behavioral models with source code, Models for synthesis, Tutorials for behavioral and synthesis modeling. assistance in development and implementation of design methodologies suitable to customer needs ******************************************************************** Saros Technology Ltd. Business and Technology Centre Stevenage Herts SG1 2DX United Kingdom Phone : ++44 (0)1438 746433 FAX: ++44 (0)1438 310093 Email : 100135.1052@compuserve.com Contact : Chris Rose Products : Saros Technology Ltd. Specialise in the provision of a complete range of VHDL development tools for the PC and Workstation platforms. As the sole UK distributor for Model Technology, Exemlar Logic and Translogic products we offer design entry, simulation and synthesis tools for FPGA and ASIC design. Saros Technology have also developed and offer a VHDL context sensitive editor for the PC under Windows. VHDL Turbo Writer comprises the powerful Codewright Editor from Premia corp, providing a fully featured, multi window, multi document text editor with line numbers and colour coding. This is enhanced by a rich set of VHDL templates, integration with the Model Technology VHDL compiler and full error detection within the editor environment. Price L495 with volume discounts for 5 or more. ******************************************************************** SEE Technologies see Summit Design. ******************************************************************** Seeds VHDL ENvironment (SVEN) Seed Solutions, Inc. 7505 Sherman Road Chesterland, OH 44026 216-729-7500 Commercial parser ******************************************************************** Seodu Logic, Inc. http://www.seodu.co.kr MyCAD PC based Toolset and Environment for VHDL Simulation, Synthesis etc. ******************************************************************** SHELOR ENGINEERING 3308 Hollow Creek Rd Arlington, TX 76017-5346 (817) 467-9367 cfshelor@acm.org (1) Training Courses (on-site and off-site offerings): Object Oriented ASIC development using VHDL based Logic Synthesis (2) Synthesizable standard components: serial interfaces, DMA, etc (3) Contracted synthesizable component development (4) Standard Behavioral Models: PowerPC, R4000, etc (5) Contracted behavioral model development (6) Beta Site evaluations for VHDL tools ******************************************************************** SICAN GmbH Garbsener Landstr. 10 39419 Hannover Phone: +49-511/277-1491 fax: +49-511/277-2490 email: info@sican.de web: http://www.sican.de USA: SICAN Microelectronics Corp. 400 Oyster Point Blvd., Suite 512 So San Francisco, CA 94080 Phone: +81-650 871-1494 fax: +81-650 871-1504 web: http://www.sican-micro.com email: info@sican-micro.com Company Overview SICAN is a microelectronic design and technology licensing company, specializing in communications, digital signal processing, multimedia and networking applications. We provide our targeted markets with leading edge design solutions by combining state-of-the-art Design Methodology with highly optimized Core Technology. VHDL Products Digital Design Services In the recent five years we have completed over 200 Digital VHDL-Designs including synthesis. You can participate in our VHDL Design Experience by realizing Turnkey Projects with us or by hiring our experienced engineers as a Consultant or as a Designer in one of your inhouse projects. In addition, you can order Training Services (VHDL, VerilogHDL, Synthesis etc.) presented by our highly experienced Senior Engineers. DesignObjectsTM SICAN's DesignObjectsTM give design teams a new alternative. Now, it is possible to buy synthesizable, technology independant cores (VHDL and/or VerilogHDL) to quickly integrate standards-based functionality required in a design. DesignObjectsTM from SICAN encompass a broad spectrum of technologies: * Audio Decoders (e. g.MPEG-2 Layer 1&2 + Dolby AC-3 5.1 Channels) * Broadband Access Functions (e. g. QAM-Demodulator) * Bus Interfaces (e. g. PCI, USB, IEEE1394, CAN Bus Controler, IIC Master / Slave Interface) * Cryptographic Functions (e. g. DVB Descrambler) * Digital Photography (e. g. JPEG Video Decoder with Color Space) * General Purpose Microcontroller (e. g. 8051 Microcontroller) * Industrial Functions (e. g. Motor Control Module, Pulse Width Modulation) * Multimedia Accelerators (e. g. Video Conferencing Hybrid Accelerator) * RAM Interfaces (e. g. SDRAM Timing Generator) * Telecommunication/Communication/ATM (e. g. UTOPIA Interface) * Video Decoders (e. g. MPEG-2 Video Decoder with Letterbox Features) * Video Encoders (e. g. MPEG-1 Video Encoder) * Video Processors (e. g. PAL/NTSC Video Encoder Interface) DesignObjectsTM can be delivered as an all-inclusive assembly of netlist or RTL source code, technical specifications, test benches, synthesis scripts and application support. Any further questions? Don't hesitate to contact us at: Phone +49-511/277-1491 or visit our web-page http://www.sican.de ******************************************************************** Silicon System Solutions P/L 2/12 Wattle Valley Road Canterbury Victoria 3126, Australia Phone: +61 3 9888 4774 Fax: +61 3 9888 4224 Email: info@silicon-systems.com WWW: http://www.silicon-systems.com Products and services * VHDL Cores (IP) Fast-track to your system integration, with a selection of Synthesis and Simulation Cores tuned to fit your needs. * FPGA and ASIC design consultants Our design experts are ready to help you with CPLD/FPGA and ASIC development. Specify the models you require, and use our design experts as a dedicated resource in your project development. * ED4W-HDL - Powerful HDL Editor for VHDL and Verilog ED4W-HDL is a VHDL/Verilog Editor for WindowsNT/95 and Windows 3.1. HDL extensions developed by ASIC/FPGA Designers at SSS, for ASIC/FPGA Designers. A very effective productivity tool. ******************************************************************** Silvar Lisco 703 E. Evelyn Avenue Sunnyvale, CA 94086 anything in VHDL? ******************************************************************** SoftSmiths Pty. Ltd. 54 Wylma St. Holland Pk. 4121 Australia Phone: + 61 7 847 2990 Fax: + 61 7 847 2707 Email: info@softsmiths.oz.au Products: VHDL Design Entry schematiX11-VHDL An X11 Sun based VHDL design entry package for the purpose of capturing VHDL designs in a graphical format and writing VHDL netlist descriptions. Being in a graphical form it is much simpler to transfer the design concepts to other colleagues and maintain the design over the life time of the product. Allows direct access to and editing of the functional code for any block at any level in the design hierarchy. Interfaces with any third party VHDL simulator. Cost effective site licences allow UNIX based productivity at prices per user comparable to PC based products. freely licenced copies of SoftSmiths' VHDLcapture tools are available for anonymous ftp download from ftp.tmx.com.au /cust/softsmiths/ Educational Licence Restrictions apply, if you are in doubt ask us first (info@softsmiths.oz.au). If you are a commercial site you may download this software for evaluation purposes. www: http://www.tmx.com.au/softsmiths/ ******************************************************************** Speed Electronic SA Puits-Godet 10a CH-2005 Neuchatel Phone: +41 327 27 7777 Fax: +41 327 27 7701 Contact: H.-D. Machuta Email: hdm@speed.ch Speed Electronic, Inc. 710 Lakeway, Suite 290 Sunnyvale, CA 94086 Phone: (408) 328 0950 Fax: (408) 328 0962 Contact: Christiane Neumann-Rivera Email: cnr@speed.com speedCHART: graphical VHDL and Verilog HDL assistant. Includes high-level schematic entry, State Diagrams, Spreadsheet and Code entry with powerful debugging facilities. Available on Sun and HP. Generates simulation and synthesis models for major VHDL and Verilog HDL simulation and synthesis tools. ******************************************************************** Summit Design, Inc. 9305 S.W. Gemini Drive Beaverton, OR 97005-7158 USA Telephone: 503-643-9281 FAX: 503-646-4954 Contact: (various) Product Name: Visual HDL Visual HDL[TM] integrates four graphical languages, a textual language, a simulator and debugger, and code generators for VHDL and Verilog. It uses a state-of-the-art, object-oriented user interface, featuring a graphical design browser. Visual HDL includes intelligent editors for input of block diagrams, state diagrams, flowcharts, and truth tables, besides VHDL text. This comprehensive set of languages helps you to work at any level of abstraction, and to mix levels of abstraction. With Visual HDL you can create a high level description of your design and validate it by execution. An event-driven, interactive simulator works in tandem with a source-level debugger for rapid analysis of the system. While the simulator runs, you can set breakpoints, modify existing signals and variables, single-step through multiple execution threads, and trace various activities. Visual feedback appears on your source descriptions, in the windows of their editors, for easy tracing. Following design verification, Visual HDL generates VHDL or Verilog code customized for the commercial synthesis tool you specify. Visual HDL is available for UNIX and for Microsoft Windows. www: extern_herf(http://www.summit-design.com/) ******************************************************************** SynaptiCAD Inc. 520 Prices Fork Rd #C4, BLACKSBURG VA 24060 USA phone: (540)953-3390 or (800)804-7073 fax: (540)953-3078, email: sales@syncad.com web: http://www.syncad.com/. SynaptiCAD develops stimulus generators and test bench generators for VHDL. SynaptiCAD's premier product TestBencher Pro, is a self-testing multi-diagram test bench generator. TestBencher Pro can detect glitches, bad logic levels, and violations of setup and hold times in simulation output. Users draw inputs to a simulation and specify expected simulation outputs using graphical constructs called samples. TestBencher Pro generates VHDL test benches with extra code which verifies that graphically-specified conditions are met by a simulator's output. Users can concatenate timing diagrams together to mimic a series of read/write bus cycles. TestBencher Pro also has looping and conditional constructs that enable simulation results to control what stimulus is applied next. SynaptiCAD also offers WaveFormer Pro, a timing diagram editor and VHDL stimulus generator. Users draw a timing diagram that represents the input to a simulation. Then the user exports the timing data as a VHDL process that contains either transport or wait statements. WaveFormer Pro supports all VHDL data types. Even user defined types like "type MyColor is (RED, BLUE, GREEN)" can be exported with both type and state information. TestBencher Pro and WaveFormer Pro are offer three different ways to enter signal waveforms: (1) a graphical environment for drawing, (2) text based temporal equations, and (3) boolean equations of other signals. Other simulator formats are also supported including Verilog, SPICE, Viewlogic, Orcad, Mentor QuickSim, and more, so timing diagrams can be reused at different times during design process. For a FREE evaluation of WaveFormer Pro, product info, and pricing, check out our web site: http://www.syncad.com/ SynaptiCAD, Inc. Sales: (800) 804-7073 P.O. Box 10608 Support: (540) 953-3390 Blacksburg, VA 24062-0608 Fax: (540) 953-3078 www: http://www.syncad.com email: syncad@swva.net ******************************************************************** Synopsys Inc. USA Synopsys, Inc. 700 East Middlefield Road Mountain View, California 94043-4033 U.S.A. Phone: (415)962-5000 FAX: (415)965-8637 Germany (moved) Synopsys, GmbH Stefan George Ring 2 D-8000 Muenchen 81 Germany Phone: 89/9939120 FAX: 89/99391217 URL: http://www.synopsys.com/ Products: Design Compiler - Constraint-Driven Logic Optimization (CMOS & GaAs) VHDL Compiler - VHDL Logic Synthesis HDL Compiler - Verilog HDL Synthesis Test Compiler - Test Synthesis (Auto. Test insertion + ATPG) VHDL System Simulator - 100% language compatible VHDL behavioral simulation ******************************************************************** Translogic Translogic BV Translogic USA Corp. Galvanistraat 14-I 1030 E. El Camino Real #430 P.O. Box 620 Sunnyvale, CA 94087 6710 BP Ede Phone: (408) 746-0707 The Netherlands Fax: (408) 746-0856 Phone: +31 (318) 642076 Email: info@translogiccorp.com Fax: +31 (318) 641761 Contact: Ella van Gool Email: info@translogic.nl Contact: Chris van Veenendaal Products: EASE/HDL: Easy to use graphical HDL entry tool. Generates VHDL and Verilog output for both simulation and synthesis purposes. Featuring hierarchy browsing and state machine diagrams. Reverse engineering, automatically generating graphical blocks for inclusion in block diagrams. EALE/HDL: Language-sensitive text editor, featuring color coding, undo/redo, multi-document edit, keyword templates, synthesis templates, completely customizable user interface and an extensive on-line help. Supports VDHL, Verilog, ABEL, C, as well as synthesis script languages. Products available on both PC and UNIX systems. For more information or a free evaluation copy please visit our web site: http://www.translogiccorp.com. ******************************************************************** The VHDL Technology Group Web: http://www.vhdl.com 100 Brodhead Road, Suite 140 Phone : 610-882-3130 Bethlehem, PA 18017 Fax : 610-882-3133 Products: a) Sledgehammer-4: Source code editor for C, C++, VHDL, Verilog b) Std_IOpak: VHDL conversion routines c) Dragster: VHDL model generation system d) Std_DevelopersKit: VHDL package set ******************************************************************** Topdown Design Solutions, Inc. 71 Spit Brook Road, Suite 301 Nashua, NH 03060 Phone: (603) 888-8811 Fax: (603) 888-7694 contact: Frank Hrobak or Art Pisani Products: VHDL SelfStart_Kit - a self-paced tutorial to learn VHDL quickly and easily, VBAK/XILINX - An Xilinx XNF to VHDL translation, which allows VHDL simulation of both pre- and post-layout designs, including full-timing simulation models. Universal DRAM VHDL source code model QuickStart, QuickStart2+1 - VHDL education at your site! Model Technology V-System VHDL Simulator - on PC/Windows and UNIX platforms Consulting + Custom Training services available, including VIP (VHDL Insertion Program) as well as public training. www: http://www.topdown.com/ ******************************************************************** TransEDA Limited Contact: Bernard Deadman, James Douglas, Martin Abrahams & Mike Stuart Address: TransEDA Limited, Pilgrim's Close, Chandler's Ford, Hants SO53 4ST, UK Phone: +44-1703-255118 (timezone GB-Eire (BST/GMT)) fax: +44-1703-270278 email: msa@transeda.demon.co.uk Products: TransGATE - VHDL Synthesis - full RTL-level VHDL support TransTEST - Test Synthesis - Scan/BIST - ATPG TransTech - Technology Remapper VeriSure - Cover coverage analysis for Verilog VHDLCover - Test-Bench Code Coverage Analyser for any simulator Training - VHDL for Logic Synthesis - public or on-site courses Services - VHDL consultancy, ASIC/FPGA design contracts ******************************************************************** Valid see CADENCE (part of) ******************************************************************** Vanilla CAD Tools, Inc. Rt. 4, Box 146 Saluda, SC 29138-9126 USA 803-445-7227 email: vanilla@emeraldis.com Vanilla VHDL is a complete implementation of the 1987 IEEE standard, including configurations. Like the old MCC system, it is completely text-based, with a gdb-like command set for its debugger/simulator. Unlike MCC, it does not translate to C, but instead uses an interpreted engine, since this simplifies debugger implementation and enhances portability. To fund further development of the tools, they are now commercially available on the PC. A 386 or better is required. An introductory price is in effect until July 30, 1995. ******************************************************************** Vantage Analysis Systems, Inc. (purchased by Viewlogic) USA: 42808 Christy Street, Suite 200 Fremont, CA 94538 phone: +1(510) 659-0901 fax: (510) 659-0129 contact: John Willey Europe: UK: Grove Court Business Centre Hatfield Road Slough Berkshire SL1 1QU (UK) France: Daniel Langois MISIL Design 2 Rue De La Couture Silic 301 94588 Rungis Cedex (France) Sweden: Lars Lindqvist :- Engineer Hardi Electronics P.O. Box 966 Varvadersvagen 4P S-220 09 Lund (Sweden) Phone +46 46 117790 Germany: Klenzestrasse 11 8045 Ismaning b. Muenchen 089/99652217 Japan: Okura & Co, Ltd 3-6 Ginza, 2 chome Chuo-ku, Tokyo 104 (JAPAN) phone: 011-81-3-566-6000, fax: 011-81-3-563-5447 Vantage Spreadsheet, 100% IEEE 1076 VHDL Source Code Debugger Concurrent Compiler Network License Integrated VHDL Schematics/Simulator Read/Write Mentor/Valid/EDIF Schematics Logic Automation & ASIC libraries Hardware Modeler On Sun & HP machines and Silicon Graphics, Apollo ******************************************************************** VAutomation Inc. 20 Trafalgar Square Suite 443 Nashua, NH USA 03063 TEL:(603)882-2282 FAX:(603)882-1587 Email: info@VAutomation.com Contact: Eric Ryherd Supplier of Technology Independent Synthesizable VHDL Models Models of complex functions such as 8-16 bit Microprocessors and their peripherals. www: http://www.vautomation.com ******************************************************************** VeriBest, Incorporated USA: 6101 Lookout Road Boulder, Colorado 80301 Phone: 303.581.2300 Fax: 303.581.9972 toll free: 800.VERIBEST WWW: http://www.veribest.com Email: info@veribest.com United Kingdom: 44.1793.511199 Germany: 49.89.96284.0 France: 33.1.41.76.35.00 Nordic: 46.8.92.54.00 Asia/Pacific: 852.2.893.3621 Japan: 81.3.3797.5277 Company: VeriBest, Inc. is a broad line supplier of EDA solutions that enable companies to solve their critical business issues by doing more and spending less. VeriBest pioneered the Windows NT EDA market by introducing its VeriBest PCB design solution in 1994 and continues to offer the best EDA price/performance available in the industry. VHDL Products: VeriBest Graphical High-Level Design: VeriBest Graphical High-Level Design is a language independent, graphical, state-machine entry and debug environment. VBGHLD includes a state table editor, a state diagram editor and a state flow graph editor. VBGHLD is integrated with VeriBest Design Capture to give you a single environment for your design definition needs. VBGHLD outputs both VHDL and Verilog. VeriBest VHDL: Introduced at DAC '96, VeriBest VHDL is a VHDL 1076-93 compliant simulator offering unique debug features such as a Network Traverser. VBVHDL is an Windows NT-product and utilizes standard NT ease-of-use features such as signal drag-n-drop into the various display and debug features. VeriBest High-Level Design: VeriBest High-Level Design is a VHDL/Verilog synthesis application that outputs VHDL and Verilog for post-synthesis simulation and outputs data for the VeriBest Design Optimizer. ******************************************************************** VHDL Technology Group 100 Brodhead Road, Suite 140 Bethlehem, PA 18017 Tel: 610-882-3130 Fax: 610-882-3133 Email: sales@vhdl.com VitalGen(tm) v1.0, a high-end model generator , produces Vital 3.0 compliant models. Sledgehammer: A language aware editor for VHDL, VERILOG, C and C++ developers. Runs under Microsoft Windows, Windows-NT and Windows-95. Provides language specific keyword identification and template expansion, keyword color coding, auto-indentation and multi-file search & replace, to name a few of the many features. Priced comparable to most PC office automation software. Std_DevelopersKit: A collection of four packages: (1) Std_IOpak: includes routines for text I/O testbench development, and type conversions. (2) Std_Mempak: routines which you can use to develop memory models. SRAMs, DRAMS, ROMS, and VRAMs. (3) Std_Regpak/Synth_Regpak: provides synthesizable datapath subprograms (4) Std_Timing: provides routines to model device timing and delays. Complements the VITAL packages. Used by over 1000 engineers worldwide. Supports: All major simulators. www: http://www.vhdl.com/ ******************************************************************** Viewlogic Systems Inc. 293 Boston Post Road West Marlboro, MA 01752 phone: 508/480-0881 or 1-800-422-4660, FAX: 508/480-0882, TELEX 174242 Germany: Viewlogic Systems GmbH Muenchner Str. 12 85744 Muenchen-Unterfoehring phone (49)-89-9572490 FAX (49)-89-95724949 Powerview - open framework based on CFI ViewSim/VHDL: simulator (behavioural and structural) ViewSynthesis, Silcsyn and ViewArchitect: FPGA, ASIC and behavioural synthesis Viewgen: schematic drawing synthesis (indirectly coupled to EDIF) Export.1076: Automatic VHDL netlist generation from Viewlogic schematic (which accepts EDIF) ViewFSM: graphical behavioral modeling tool that allows you to draw statecharts and automatically produce VHDL for simulation and VHDL that is optimized for synthesis ******************************************************************** Vista Technologies, Inc. USA: 1100 Woodfield Road, Suite 437 Schaumburg, IL 60173-5121 phone: (708) 706-9300, fax: (708) 706-9317 contact: David Jakopac email: hdlinfo@vistatech.com Japan: Marubeni Hytech Corp. Marubeni Hytech Bldg. 20-22, Koishikawa 4-Chome Bunkyo-ku, Tokyo 112 JAPAN phone: 81-3-3817-4871, fax: 81-3-3817-4880 contact: Ken Sakamaki Europe: LEDA S.A. Europarc, Bat. C F-13013 Marseille FRANCE phone: 33+ 91 06 26 73, fax: 33+ 91 06 24 66 contact: Olivier Thibault All of Vista's tools generate VHDL suitable for simulation, with optional generation specifically for synthesis. All of Vista's tools allow users to import VHDL Packages so that custom types, functions and procedures can be utilized. StateVision: Graphical state machine editor. Generates VHDL from bubble diagrams of concurrent state-machines for simulation or synthesis. Open and customizable system. Can be integrated with off-the-shelf VHDL simulators for a complete design and debug environment (set breakpoints in states, step with animation, etc.) Shipping 4Q94. DesignVision: Graphical behavior modeling editor. Uses the DesignVision methodology ("threads") for specifying behavior graphically. Generates VHDL for simulation or synthesis. Open and customizable system. Users can customize the generated VHDL to their own style and build their own graphical primitives (including how the primitives generate VHDL). Can be integrated with off-the-shelf VHDL simulators for a complete design and debug environment (set breakpoints in threads, step with animation, etc.) Special introductory price through Oct. '94. Shipping now. Vista Model Creator: Spreadsheet-like interface that generates VHDL from function and state machine tables for simulation or synthesis. Compact representation ideal for ALUs, instruction decoders, etc. Shipping now. VHDL Language Assistant: Syntax-directed editor with built-in knowledge of VHDL. Not just language templates, full VHDL-1076 built-in. No special representation: can read, edit and write any VHDL file. Shipping now. The VHDL Developer: Suite of tools that includes VHDL Language Assistant and Source Code Library Manager. Shipping now. The VHDL Developer Plus: Suite of tools that includes Vista Model Creator, VHDL Language Assistant, and Source Code Library Manager. Shipping now. ******************************************************************** Vital, Inc. 4109 Candlewyck Drive Plano, TX 75024 U.S.A Ph: +1 (214) 491-6907 Fax: +1 (214) 491-6909 Email: info@vital.com or owner-crisp-list@uunet.uu.net CRiSP is a graphical file editor on various UNIX and Windows platforms, which combines the power and flexibility of other editors such as vi, or Emacs but in a user-friendly fashion. CRiSPs' dynamic syntax coloring for VHDL adds a new dimension to the coding cycle. You can print the VHDL code in color too !!. The editor comes with advanced template editing for VHDL, and has an extensible macro language to customize it to the users environment. ******************************************************************** VIZEF Limited The Old Coach House Adwell Thame OXON Tel: 44 (0)1844 281066 Fax: 44 (0)1844 281070 Email: steve@vizef.demon.co.uk SpeedSim high speed cycle simulation for fast verification of RTL Verilog. Typically 10-100 times faster than Verilog-XL. Virtual-ICE, for co-verification of hardware and firmware. This tool enables ASIC/Software designers to run their firmware with the RTL level ASIC and a CPU/DSP core(s) of choice. Using this tool allows you to start final firmware debug and software performance analysis before a physical device (FPGA or engineering samples) is available. FlowHDL graphical tool for RTL design and testbench capture using the ASM methodology. VHDL and Verilog output targeted for user specified synthesis environment. Design environment supports multiple interacting state machines, data path specification, multiple clock domains, sync/async reset specification, synthesis directives and much more. ******************************************************************** Walnut Creek CDROM 4041 Pike Lane, Suite E Concord, CA 94520 800/786-9907 or 510/674-0783 FAX 510/674-0821 Email info@cdrom.com ADA CDROM has (besides other stuff) uc -- the University of Cincinnati VHDL repository VHDL (VHSIC Hardware Description Language) Vhdl Mailing list moved to vhdl-sw@ece.uc.edu. All messages to the list will be automatically archived on ftp.ece.uc.edu. These messages are located in /pub/mailing-lists/vhdl-sw directory. ftp Archive moved to thor.ece.uc.edu Eventually, the ftp archive will be moved to ftp.ece.uc.edu too. NEW SUBSCRIPTIONS SHOULD BE SENT TO listserver@ece.uc.edu. THE BODY OF THE MESSAGE SHOULD BE AS FOLLOWS: subscribe vhdl-sw Your-name ******************************************************************** X-Tek Engineering X-HDL, Verilog to VHDL translator. X-HDL has the power to perform 100% translation of your synthesizable Verilog code to VHDL. Also X-HDL can translate non-synthesizable constructs such as delay statements and display statements, with additional support coming in the near future. X-HDL has an intuitive, X-Windows based user interface. DEMO VERSIONS OF X-HDL FOR SUN AND HP PLATFORMS ARE NOW AVAILABLE VIA http://www.x-tekcorp.com/download.htm For additional information, send your request to: thomasr@mail.msen.com www: http://www.x-tekcorp.com/ ******************************************************************** Zycad Corporation (ZyCads VHDL SOFTware was sold to Synopsys) 47100 Bayside Parkway Fremont, CA 94538-9942 USA phone: 1(510)623-4400 fax: 1(510)623-4550 VIP VHDL Instruction Processor hardware accelerators ********************************************************************
The following lists are (probably) incomplete. Therefore, if you have any additional information or find any errors or compiler missing: please send me a note. Further, if anyone has good or bad experiences with this tools (particularly with free software) please let me know. Thanks for all corrections.
Here is what's currently available:
The commercial compilers are divided into three price categories:
| Price category | Range (USD) |
| A | $1 < $200 |
| B | $200 < $1000 |
| C | above $1000 |
See also section 2. Companies and their products/services for additional information.
See also section 2. Companies and their products/services for additional information.