Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity tb_rsa is end; architecture tb of tb_rsa is component rsa port( reset : in std_logic; clk : in std_logic; new_key : in std_logic; new_mod : in std_logic; new_data : in std_logic; data_in : in std_logic_vector(10 downto 0); data_out : out std_logic_vector(10 downto 0); ready : out std_logic ); end component; signal reset, clk, new_key, new_mod, new_data, ready : std_logic; signal data_in, data_out, daten : std_logic_vector(10 downto 0); begin my_rsa: rsa port map(reset, clk, new_key, new_mod, new_data, data_in, data_out, ready); load_pro: process begin daten <= "00000000000"; data_in <= "XXXXXXXXXXX"; new_key <= '0'; new_mod <= '0'; new_data <= '0'; wait for 800 ns; -- Modulus k = 1961 data_in <= "11110101001"; new_mod <= '1'; wait for 100 ns; new_mod <= '0'; wait for 200 ns; -- Schluessel y = 1019 data_in <= "01111111011"; new_key <= '1'; wait for 100 ns; new_key <= '0'; wait for 200 ns; for i in 0 to 1024 loop data_in <= daten; new_data <= '1'; wait for 100 ns; new_data <= '0'; wait for 200 ns; daten <= daten + '1'; data_in <= "XXXXXXXXXXX"; wait on ready; wait for 200 ns; end loop; end process; clk_pro: process -- 10 MHz Takt begin clk <= '0'; wait for 50 ns; clk <= '1'; wait for 50 ns; end process; reset_pro: process begin reset <= '0'; wait for 444 ns; reset <= '1'; wait; end process; end tb; configuration cfg_tb_rsa of tb_rsa is for tb end for; end;