-- -----------------------------------------------------------------------------
--  FLEXA - ENTITY to for instansiation within EPF10K10LC84B top level entity -- 
-- -----------------------------------------------------------------------------
--
--  File        : 'flexb.vhd'
--  Author      :  Lars Larsson 
-- 
--  Date        : January 22, 1999
--
--  Description : This is a design frame - the top level design for synthesis -
--                for your own designs provided for the Altera EPF10K10LC84-3
--                FPGA. The data sheet of this FPGA is available worldwide 
--                under http://www.altera.com/ and locally (domain 
--                informatik.uni.hamburg.de) under http://tech-www/00sheets/
--
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--                                  http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- -----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- use work.components.all;                -- YOUR COMPONENT DEFINITION PACKAGE
   use work.chips.all;                     -- EPLD and FPGA definition package

   entity flexb is                         -- Flex10K FPGA B (RSA processor)
     port(       
                  clk :    in std_logic;   -- clock = 16 MHz quartz oscillator
                 nrst :    in std_logic;   -- *reset (automatic power-on reset)

        nsend_receive :    in std_logic;   -- send/receive selection (0:send,1:receive)

              request :    in std_logic;   -- request to process (=>send) 
                 send :   out std_logic;   -- start sending      (=>request) 

                 hold :    in std_logic;   -- hold (not enable)  (=>busy) 
                 busy :   out std_logic;   -- busy indicator     (=>hold) 

              char_in :  in std_logic_vector (7 downto 0); -- input data stream
             char_out : out std_logic_vector (7 downto 0); -- output data stream

              data_in :    in std_logic;   -- busy indicator
             data_out :   out std_logic    -- busy indicator
         );
   end flexb;

   architecture structure of flexb is

   -- signal z,b : std_logic; 

     begin
          
        -- compressor_i : compressor port map ( -- port => signal/port 
        --                                         clk => clk, nrst => nrst, 
        --                                                                 
        --                                    );

   end structure;

-- -----------------------------------------------------------------------------

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