-- ----------------------------------------------------------------------------- -- EPLD - ENTITY to for instansiation within LEVEL ENTITY frame design for our FPGA-Praktikum -- -- ----------------------------------------------------------------------------- -- -- File : 'epld.vhd' -- Author : Lars Larsson -- -- Date : January 21, 1999 -- -- Description : This is a design frame - the top level design for synthesis - -- for your own designs provided for the in-system programmable -- Altera EPM7160SLC-15 EPLD. The data sheet of this EPLD is -- available worldwide under http://www.altera.com/ and locally -- (domain informatik.uni.hamburg.de) under http://tech-www/00sheets/ -- -- ----------------------------------------------------------------------------- -- -- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science -- University of Hamburg -- Vogt-Koelln-Str. 30 -- D - 22041 Hamburg, Germany -- larsson@informatik.uni-hamburg.de -- http://tech-www.informatik.uni-hamburg.de/~larsson -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -- -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.chips.all; use work.components.all; entity epld is port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset -- baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) -- rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100 irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100 -- nkey : in std_ulogic; -- strobe key (push down = '0', up = '1') dip_switches : in std_ulogic_vector ( 7 downto 0); -- DIP-Switches 1-2-3-4-5-6-7-8 -- idata : in std_ulogic_vector ( 7 downto 0); -- data bus input (if nwe='1') odata : out std_ulogic_vector ( 7 downto 0); -- data bus output (if nwe='0') address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 for SRAM xOR DRAM nwe : out std_ulogic; -- read / write selector for RAM (not write enable) -- ncs : out std_ulogic; -- not Chip Select of SRAM -- nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM ncas : out std_ulogic; -- not Column Address Strobe (nCAS) of DRAM type_of_ram : out ram_type -- {SRAM,DRAM} ); end epld; architecture structure of epld is -- STANDARD SIGNAL DEFINITIONS HERE ----------------------------------------------------------------- signal clk_s, nrst_s : std_ulogic; -- clock and reset signal signal rs232_txd_s, rs232_rxd_s : std_ulogic; -- RS232 signals signal irda_rxda_s, irda_txd_s : std_ulogic; -- IrDA signals signal baud_clk_x16_s, baud_clk_s : std_ulogic; -- baud clock signals signal nsend_receive_s : std_ulogic; -- nsend_receive selection signal signal baud_rate_select_s : std_ulogic_vector (2 downto 0); -- baud rate selection signals signal dip_switches_s : std_ulogic_vector (7 downto 0); -- 8 x DIP switch (blue) signal nkey_s : std_ulogic; -- strobe key (white) signal idata_s, odata_s : std_ulogic_vector ( 7 downto 0); -- RAM data bus RAM->idata, odata->RAM signal address_s : std_ulogic_vector (10 downto 0); -- address bus signal nwe_s : std_ulogic; -- write enable signal for SRAM & DRAM signal ncs_s : std_ulogic; -- SRAM chip select signal signal nras_s : std_ulogic; -- DRAM row address stobe signal signal ncas_s : std_ulogic; -- DRAM column address strobe signal signal busy_s : std_ulogic; -- Busy signal of RS232 interface signal akn_s : std_ulogic; -- acklowledge signal of RS232 interface type ram_type is ( SRAM, DRAM ); signal ram : ram_type; -- --------------------------------------------------------------------------------------------------------- -- ADDITIONAL HELPER SIGNAL DEFINITIONS HERE --------------------------------------------------------------- signal rs232sender_txd_s, txd_s : std_ulogic; -- additional TxD signals signal send_s : std_ulogic; -- send signal (not nkey_s) signal led_data_s : std_ulogic_vector(7 downto 0); -- LEDs or buffered data to data bus (odata) -- --------------------------------------------------------------------------------------------------------- -- DEFINE YOUR OWN ADDITIONAL INTERNAL SIGNALS HERE -------------------------------------------------------- -- signal my_signal_s : std_logic; -- just an example -- signal my_signal_vector_s : std_logic_vector (7 downto 0); -- just one more example -- --------------------------------------------------------------------------------------------------------- -- BEGIN OF ARCHITECTURE ----------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------------------------------- begin -- ------------------------------------------------------------------------------------------------------ -- DEFINITION OF RAM TYPE ------------------------------------------------------------------------------- ram <= SRAM; -- ------------------------------------------------------------------------------------------------------ -- CONNECT INTERNAL SIGNALS TO PORTS OF THE ENTITY EPLD ------------------------------------------------- ------------------------------------------------------------------------------------------------------ -- INPUTS -------------------------------------------------------------------------------------------- clk_s <= clk; nrst_s <= nrst; baud_rate_select_s <= baud_rate_select; nsend_receive_s <= nsend_receive; rs232_txd_s <= rs232_txd; irda_rxda_s <= irda_rxda; nkey_s <= nkey; dip_switches_s <= dip_switches; idata_s <= idata; type_of_ram <= SRAM; ------------------------------------------------------------------------------------------------------ -- OUTPUTS ------------------------------------------------------------------------------------------- rs232_rxd <= rs232_rxd_s; irda_txd <= irda_txd_s; nwe <= nwe_s; ncs <= ncs_s; nras <= nras_s; ncas <= ncas_s; address <= address_s; odata <= odata_s; -- ------------------------------------------------------------------------------------------------------ -- ALL UNUSED OUTPUT SIGNALS MUST BE DRIVEN ------------------------------------------------------------- address_s <= "00000000000"; nwe_s <= '0'; ncs_s <= '1'; nras_s <= '1'; ncas_s <= '1'; -- rs232sender_txd_s <= '1'; -- ------------------------------------------------------------------------------------------------------ -- PORT MAPPING OF YOU OWN INSTANCES -------------------------------------------------------------------- txd_s <= rs232_txd_s AND rs232sender_txd_s; odata_s<= led_data_s; irda_codec_i : irda_codec port map ( -- port => signal clk => clk_s, nrst => nrst_s, baud_rate_select=>baud_rate_select_s, nsend_receive=>nsend_receive_s, rs232_txd=>txd_s, rs232_rxd=>rs232_rxd_s, irda_rxda=>irda_rxda_s, irda_txd=>irda_txd_s, baud_clk_x16=>baud_clk_x16_s, baud_clk=>baud_clk_s ); rs232receiver_i : rs232receiver port map ( clk => clk_s, nrst => nrst_s, baud_clk_x16=>baud_clk_x16_s, rxd => rs232_rxd_s, dout => led_data_s, -- busy => busy_s, akn => akn_s ); send_s <= not nkey_s; rs232sender_i : rs232sender port map ( clk => clk_s, nrst => nrst_s, baud_clk => baud_clk_s, request => send_s, din => dip_switches_s, busy => busy_s, txd => rs232sender_txd_s ); end structure; -- --------------------------------------------------------------------------------------------------------- -- END OF ARCHITECTURE ------------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------------------------------