-- --------------------------------------------------------------------------- -- IrDA, RS232, TEXT_BUFFER component definitions -- PACKAGE -- -- --------------------------------------------------------------------------- -- -- File : 'components.vhd' -- Author : Lars Larsson -- -- Date : February 8, 1999 -- -- --------------------------------------------------------------------------- -- -- Copyright (C) 1998 Lars Larsson, Dept. of Computer Science -- University of Hamburg -- Vogt-Koelln-Str. 30 -- D - 22041 Hamburg, Germany -- larsson@informatik.uni-hamburg.de -- http://tech-www.informatik.uni-hamburg.de/~larsson -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -- -- --------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package components is component irdafuse port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset txdin : in std_ulogic; -- IrDA TXD signal (high active) txdout : out std_ulogic; -- fused IrDA TXD signal alive : out std_ulogic; -- assumed that infrared emitter diode is ok (GREEN LED) killed : out std_ulogic; -- fuse locked, IR LED would have been killed (RED LED) revival : in std_ulogic -- revive fused IrDA signal, wiht a pull up Resisor R, -- irda fuse unlocks automatically after resting state ); end component; component irda_codec port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection inputs nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from IrDA tranceiver (eg. HP HSDL-1100) irda_txd : out std_ulogic; -- TXD-A (IrDA 1.0 & 1.1) signal to IrDA tranceiver (eg. HP HSDL-1100) baud_clk_x16 : out std_ulogic; -- baud rate clock times 16 output baud_clk : out std_ulogic -- baud rate clock output ); end component; component irda_codec_fused port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection inputs nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from IrDA tranceiver (eg. HP HSDL-1100) irda_txd : out std_ulogic; -- FUSED TXD (IrDA 1.0 & 1.1) signal to IrDA tranceiver (eg. HP HSDL-1100) baud_clk_x16 : out std_ulogic; -- baud rate clock times 16 output baud_clk : out std_ulogic; -- baud rate clock output alive : out std_ulogic; -- assumed that infrared emitter diode is ok (GREEN LED) killed : out std_ulogic; -- fuse locked, IR LED would have been killed (RED LED) revival : in std_ulogic -- revive fused IrDA signal, with a pull up resistor R, -- it unlocks automatically after resting state ); end component; -- ------------------------------------------------------------------------------- component rs232sender port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset baud_clk : in std_ulogic; -- baud rate clock input request : in std_ulogic; -- 0-1-0-transition sends din din : in std_ulogic_vector (7 downto 0); -- data byte to send busy : out std_ulogic; -- busy='1' while sending data txd : out std_ulogic -- rs232 TxD serial data output ); end component; component rs232receiver port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset baud_clk_x16 : in std_ulogic; -- baud rate times 16 clock input rxd : in std_ulogic; -- rs232 RxD serial data input dout : out std_ulogic_vector (7 downto 0); -- data byte received busy : out std_ulogic; -- busy='1' while receiving data akn : out std_ulogic -- acknowledge pulse ); end component; -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - component text_buffer port( clk : in std_ulogic; -- clock = 16 MHz nrst : in std_ulogic; -- *reset din : in std_ulogic_vector ( 7 downto 0); -- data byte input request : in std_ulogic; -- transition (0-1-0) requests memory cycle dout : out std_ulogic_vector ( 7 downto 0); -- data byte output hold : in std_ulogic; -- hold text_buffer procesing busy : out std_ulogic; -- busy indicator io_busy : in std_ulogic; -- while io_busy='1' external IO (RAM) in progress send : out std_ulogic; -- send -> request (0-1-0) if dout is valid nwe : out std_ulogic; -- NOT write enable to RAM ncs : out std_ulogic; -- NOT chip select to RAM nrefresh : out std_ulogic; -- NOT force refresh cycle (DRAM only) buffer_address : out std_ulogic_vector (10 downto 0); -- buffer address (to external RAM) idata : in std_ulogic_vector ( 7 downto 0); -- input data from RAM data bus odata : out std_ulogic_vector ( 7 downto 0) -- out data to RAM data bus ); end component; -- ------------------------------------------------------------------------------- end components; package body components is end components; -- -------------------------------------------------------------------------------