-- --------------------------------------------------------------------------- -- SRAM 61256 (32Kx8) - Simplified behavioral SRAM -- TEST BENCH -- -- --------------------------------------------------------------------------- -- -- File : 'sram61256_testbench.vhd' -- Author : Lars Larsson -- -- Date : February 15, 1999 -- -- Description : The design is a behavioral SRAM model 61256 (MSM52256, ...) -- -- Hint : Package simulation (file 'simulation.vhd') is required. Run -- simulation over 1000 ns. -- -- ----------------------------------------------------------------------------- -- -- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science -- University of Hamburg -- Vogt-Koelln-Str. 30 -- D - 22041 Hamburg, Germany -- larsson@informatik.uni-hamburg.de -- http://tech-www.informatik.uni-hamburg.de/~larsson -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -- -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.simulation.all; entity sram61256_testbench is end sram61256_testbench; architecture simulate of sram61256_testbench is constant T_AA : time := 15 ns; -- Address Acces Time constant T_CO : time := 15 ns; -- nCS Access Time signal address_s : std_logic_vector (14 downto 0); signal data_s, idata_s, odata_s : std_logic_vector (7 downto 0); signal nwe_s,ncs_s,noe_s : std_logic; -- signal t_access : time := 0 ns; begin tristate_p : process ( odata_s, nwe_s, noe_s ) begin if (nwe_s='0') then data_s <= odata_s; else data_s <= (others=>'Z'); end if; end process; idata_s <= data_s; sim_p : process begin noe_s<='0'; nwe_s<='1'; ncs_s<='1'; address_s<="000000000000000"; odata_s<="00000000"; wait for 100 ns; nwe_s<='0'; ncs_s<='1'; address_s<="000000000000000"; odata_s<="00000000"; wait for 100 ns; ncs_s<='0'; wait for 20 ns; nwe_s<='0'; ncs_s<='1'; address_s<="000000000000001"; odata_s<="00000001"; wait for 100 ns; ncs_s<='0'; wait for 20 ns; ncs_s<='1'; wait for 20 ns; nwe_s<='1'; ncs_s<='1'; address_s<="000000000000000"; odata_s<="00000000"; wait for 100 ns; ncs_s<='0'; wait for 20 ns; nwe_s<='1'; ncs_s<='1'; address_s<="000000000000001"; odata_s<="00000000"; wait for 100 ns; ncs_s<='0'; wait for 20 ns; nwe_s<='1'; ncs_s<='1'; address_s<="000000000000010"; odata_s<="00000000"; wait for 100 ns; ncs_s<='0'; wait for 20 ns; nwe_s<='1'; ncs_s<='1'; address_s<="000000000000011"; odata_s<="00000000"; wait for 100 ns; wait; end process; sram_i : sram61256 port map ( nwe_s,ncs_s,noe_s,address_s,data_s ); end simulate; -- ============================ CONFIGURATION ============================ configuration sram61256_testbench_cfg of sram61256_testbench is for simulate end for; end sram61256_testbench_cfg; -- ======================== END OF CONFIGURATION =========================