-- -----------------------------------------------------------------------------
--  IRDA2RXD - a IrDA 1.0 signal to RS232 TxD decoder           -- TEST BENCH --
-- -----------------------------------------------------------------------------
--
--  File        : 'irda2rxd.vhd'
--  Author      :  Lars Larsson 
-- 
--  Date        :  February 15, 1999
--
--  Description :  This is an example test bench for the 'irda2rxd.vhd'.
--
--  Hint        :  Package simulation (file 'simulation.vhd') is required.
-- 
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--                                  http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- -----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use work.simulation.all;

entity irda2rxd_testbench is
end irda2rxd_testbench;

architecture simulate of irda2rxd_testbench is

   constant  T_BAUD : time := 104167 ns; -- 1 / 9600 bps = 104.16666666 us

   signal t_s                                   : time := T_BAUD; 
   signal txd_s, irda_txd_s, irda_rxda_s, rxd_s : std_ulogic;

   signal HelloSUB : string (1 to  7) := "Hello!" & SUB; -- SUB = ^Z

   begin

           s2txd_i : string2txd port map (t_s,HelloSUB,txd_s);
        txd2irda_i : txd2irda port map (t_s,txd_s,irda_txd_s);

        irda_rxda_s <= not irda_txd_s after 0 us, '1' after 2.2 us; -- HSDL-1100

        irda2rxd_i : irda2rxd port map (t_s,irda_rxda_s,rxd_s);

   end simulate;

-- -----------------------------------------------------------------------------

configuration irda2rxd_testbench_cfg of irda2rxd_testbench is
  for simulate
  end for;
end irda2rxd_testbench_cfg;

-- -----------------------------------------------------------------------------

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