Integrated Device Technology Models

This page contains a brief description of the Integrated Device Technology VHDL models and pointers to the source files.

Package header and body (Here) for Integrated Device Technology models: Description : Utility package for all Integrated Device; Technology models; General Taxonomy Level : Behavioral; Created by : Mississippi State University
IDTXXFCT543 (Here): Description : Octal Latched Transceiver w/ Latch Enable,; Chip Enable, and Output Enable; General Taxonomy Level : Full Functional; Created by : Mississippi State University
IDTXXFCT646 (Here): Description : Octal Transceiver/Register w/ Enable and; Direction Control; General Taxonomy Level : Full Functional; Created by : Mississippi State University
IDTXXFCT841 (Here): Description : High-Performance CMOS Bus Interface; Latch(es); General Taxonomy Level : Full Functional; Created by : Mississippi State University