use work.Basic.all;

package RBMULTpack is

---------------------------------------------------------------
-- Behavioral Description of the Multiplication ---------------
---------------------------------------------------------------

component RBMULTbehave
  port (A,B: in Integer;P: out Integer);
end component;

---------------------------------------------------------------
-- Structural Description of "Russische Bauernmultiplikation --
---------------------------------------------------------------

component RBMULTstruc
  generic (N: Positive;Time_flag: Delay_flag);
  port (A,B: in Logic_vector(N-1 downto 0);req,clk: in Logic;
        Pout: out Logic_vector(2*N-1 downto 0);f: out Logic);
end component;

---------------------------------------------------------------
-- The following components are needed for Structural ---------
-- Descriprtion -----------------------------------------------
---------------------------------------------------------------

component RBMULTctrl
  generic (Time_flag: Delay_flag);
  port (req,f1,clk: in Logic;init,f,load: out Logic);
end component;

component expand
  generic (N,M: Positive;Time_flag: Delay_flag);
  port (X: in Logic_vector(N-1 downto 0);
        Y: out Logic_vector(M-1 downto 0));
end component;

end RBMULTpack;

---------------------------------------------------------------
-- VHDL Descriptions ------------------------------------------
---------------------------------------------------------------

entity RBMULTbehave is
  port (A,B: Integer;P: out Integer);
end RBMULTbehave;

architecture Behavior of RBMULTbehave is
begin

  p0: process
  begin
    P <= A*B;
    wait on A,B;
  end process;

end Behavior;

use work.Basic.all;
use work.Elementary.all;
use work.RBMULTpack.all;

entity RBMULTstruc is
  generic (N : Positive;Time_flag : Delay_flag);
  port (A,B: in Logic_vector(N-1 downto 0);req,clk : in Logic;
        Pout: out Logic_vector (2*N-1 downto 0);f : out Logic);
end RBMULTstruc;

architecture Structure of RBMULTstruc is
  signal A_expand,L1,R2,L3,L6,L7,P: Logic_vector(2*N-1 downto 0);
  signal R3,L4,L5: Logic_vector(N-1 downto 0);
  signal I1,I2,load,init,f1,zero : Logic;
begin

  logic_level : LOG2
    port map(open,zero);

  buffer_Pout : nBUF
    generic map(2*N,Time_flag)
    port map(P,Pout);

  expand_A : expand
    generic map(N,2*N,Time_flag)
    port map(A,A_expand);

  MUX_A : nMUX
    generic map(2*N,Time_flag)
    port map(L3,A_expand,init,L1);

  REG_A : nREG
    generic map(2*N,Time_flag)
    port map(clk,load,L1,R2);

  SHIFT_A : nLSH
    generic map(2*N,Time_flag)
    port map (R2,zero,L3,I1);

  ADD_A_OUT : CRA
    generic map(2*N,Time_flag)
    port map(R2,P,zero,L7,open);

  MUX_OUT : nMUX
    generic map(2*N,Time_flag)
    port map(P,L7,I2,L6);

  REG_OUT : nREGr
    generic map(2*N,Time_flag)
    port map(clk,load,init,L6,P);

  MUX_B : nMUX
    generic map(N,Time_flag)
    port map(L5,B,init,L4);

  REG_B : nREG
    generic map(N,Time_flag)
    port map(clk,load,L4,R3);

  CMP0_B : nCMP0
    generic map(N,Time_flag)
    port map(R3,f1);

  SHIFT_B : nRSH
    generic map(N,Time_flag)
    port map(R3,zero,L5,I2);

  Controller : RBMULTctrl
    generic map(Time_flag)
    port map (req,f1,clk,init,f,load); 

end Structure;

use work.Basic.all;
use work.Elementary.all;

entity RBMULTctrl is
  generic (Time_flag: Delay_flag);
  port (req,f1,clk: in Logic;init,f,load: out Logic);
end RBMULTctrl;

architecture Structure of RBMULTctrl is
  signal not_f,or1_out,or2_out,not_load,Q,QZ: Logic;
begin

  or_gate1 : OR2
    generic map(Time_flag)
    port map(req,not_f,or1_out);

  state : DFF
    generic map(Time_flag)
    port map(or1_out,clk,Q);

  inv_gate1 : INV
    generic map(Time_flag)
    port map(Q,QZ);

  or_gate2 : OR2
    generic map(Time_flag)
    port map(QZ,f1,or2_out);

  inv_gate2 : INV
    generic map(Time_flag)
    port map(or2_out,not_f);

  and_gate : AND2
    generic map(Time_flag)
    port map(req,or2_out,init);

  buf_gate1 : BUF
    generic map(Time_flag)
    port map(or2_out,f);

  buf_gate2 : BUF
    generic map(Time_flag)
    port map(Q,load);

end Structure;

use work.Basic.all;

entity expand is
  generic(N,M: Positive;Time_flag: Delay_flag);
  port(X: in Logic_vector(N-1 downto 0);
       Y: out Logic_vector(M-1 downto 0));
end expand;

architecture Behavior of expand is
begin

  P0: process
  begin
    Loop0:
    for I in 0 to M-1 loop
      if I<N  
        then Y(I) <= X(I);
        else Y(I) <= '0';
      end if;
    end loop Loop0; 
    wait on X;
  end process;

end Behavior;

---------------------------------------------------------------
-- Testbench --------------------------------------------------
---------------------------------------------------------------

use work.Basic.all;
use work.RBMULTpack.all;

entity Test_RBMULT is end Test_RBMULT;

architecture Test of Test_RBMULT is

  constant N: Positive := 4; -- data word length

  signal A,B,P: Integer;
  signal Avec,Bvec: Logic_vector(N-1 downto 0);
  signal Pvec: Logic_vector(2*N-1 downto 0);
  signal req,clk,f: Logic := '0';

begin

  Implementation : RBMULTstruc
    generic map(N,Const_delay)
    port map (Avec,Bvec,req,clk,Pvec,f);

  Specification : RBMULTbehave
    port map (A,B,P);

A <= 0 after 0Ns, 15 after 80Ns;
B <= 0 after 0Ns, 14 after 80Ns;

Avec <= "0000" after 0 Ns, "1111" after 80 Ns, "0000" after 120 Ns;
Bvec <= "0000" after 0 Ns, "1110" after 80 Ns, "0000" after 120 Ns;

req <= '0' after 0 Ns, '1' after 80 Ns, '0' after 120 Ns;

clk <= '0' after    0 Ns, '1' after 100 Ns,
       '0' after  200 Ns, '1' after 300 Ns,
       '0' after  400 Ns, '1' after 500 Ns,
       '0' after  600 Ns, '1' after 700 Ns,
       '0' after  800 Ns, '1' after 900 Ns,
       '0' after 1000 Ns;

end Test;