--==========================================================
-- Design units : MinMaxStruc (Entity,Architecture,Configuration)
--
-- File name    : MinMax_Structure.vhd
--
-- Purpose      : Top-level entity of the MinMax-Circuit
--
-- Limitations  :
--
-- Library      : WORK
--
-- Dependencies : ELEMpack,MinMax_LastValue,MinMax_MeanValue,
--                MinMax_3_to_4
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    13.12.95       new
--=========================================================

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.MinMaxPack.all;

ENTITY MinMaxStruc IS
  GENERIC(M : positive := 4);
  PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
       Enable     : IN std_logic;
       Clk        : IN std_logic;
       Clear      : IN std_logic;
       Reset      : IN std_logic;
       DataOut    : OUT std_logic_vector(M-1 DOWNTO 0));

END MinMaxStruc;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF MinMaxStruc IS

  SIGNAL condition_1,condition_2,condition_3,condition_4,and_out_1: std_logic;
  SIGNAL last_out,mean_out,and_out_2,and_out_3,and_out_4:std_logic_vector(M-1 DOWNTO 0);
  SIGNAL zero: std_logic :='0';
  
  BEGIN

    conditions: Three_to_four
      PORT MAP(Clear,Enable,Reset,
               condition_1,condition_2,
               condition_3,condition_4);

    Memory_input: Last
      GENERIC MAP(M)
      PORT MAP(DataIn,Enable,Clk,last_out); 

    m_value: Mean_value
      GENERIC MAP(M)
      PORT MAP(DataIn,Reset,Clk,mean_out);

    Gate_1: AND2
      PORT MAP(zero,condition_1,and_out_1);

    and_2: FOR I IN M-1 DOWNTO 0 GENERATE
            G_AND_I_2: AND2
              PORT MAP(condition_2,last_out(I),and_out_2(I));
          END GENERATE;

    and_3: FOR I IN M-1 DOWNTO 0 GENERATE
            G_AND_I_3: AND2
              PORT MAP(condition_3,DataIn(I),and_out_3(I));
          END GENERATE;

    and_4: FOR I IN M-1 DOWNTO 0 GENERATE
            G_AND_I_4: AND2
              PORT MAP(condition_4,mean_out(I),and_out_4(I));
          END GENERATE;

    or_four: FOR I IN M-1 DOWNTO 0 GENERATE
               G_or_I: OR_4
                 PORT MAP(and_out_1,and_out_2(I),and_out_3(I),and_out_4(I),DataOut(I));
             END GENERATE;


END Structure;

--============================CONFIGURATION=================

CONFIGURATION MinMaxStruc_Config OF MinMaxStruc IS

FOR Structure

  FOR conditions: Three_to_four
    USE ENTITY work.three_to_four(Structure);
  END FOR;

  FOR Memory_input: Last
    USE ENTITY work.Last(Structure);
  END FOR;

  FOR m_value: Mean_value
    USE ENTITY work.Mean_value(Structure);
  END FOR;

  FOR all : AND2
    USE ENTITY work.and2(Behavior);
  END FOR;

  FOR and_2
    FOR all: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;
  END FOR;

  FOR and_3
    FOR all: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;
  END FOR;

  FOR and_4
    FOR all: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;
  END FOR;

  FOR or_four
    FOR all: OR_4
      USE ENTITY work.or_4(Behavior);
    END FOR;
  END FOR;

END FOR;

END MinMaxStruc_Config;