--==========================================================
-- Design units : FiFoStage
--
-- File name    : FIFOstage.vhd
--
-- Purpose      : Implementation of one stage for FIFO
--
-- Limitations  : none
--
-- Library      : work
--
-- Dependencies : FIFOpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95
-- V2.0    cjt    16.11.95       std_logic, configuration, ESA-standard
--===========================================================
-- Note: This description takes reference to the file FIFOpack, in which 
--       some of the gates already implemented in ELEMpack are modified
--       by using a delay time. Take care to use these for simulation,
--       since otherwise the simulation will not work due to the feedback
--       loop in FIFOstage.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;


ENTITY FIFOstage IS

  GENERIC (M: Positive := 4);
  PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
       ShiftIn    : IN std_logic;
       ShiftOut   : IN std_logic;
       MasterReset: IN std_logic;
       DataOut    : OUT std_logic_vector(M-1 DOWNTO 0);
       InputReady : OUT std_logic;
       ClockPulse : OUT std_logic;
       OutputReady: OUT std_logic);

END FIFOstage;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF FIFOstage IS

  SIGNAL clk,QZ,Q: std_logic := '0';

BEGIN

  Memory: nREG
    GENERIC MAP(M)
    PORT MAP(clk,clk,DataIn,DataOut);

  Connect: AND2
    PORT MAP(ShiftIn,QZ,clk);

  State: RSFFR
    PORT MAP(clk,ShiftOut,MasterReset,Q,QZ);

  Out0: Buf
    PORT MAP (clk,ClockPulse);

  Out1: Buf
    PORT MAP (QZ,InputReady);

  Out2: Buf
    PORT MAP (Q,OutputReady);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION FIFOstage_config OF FIFOstage IS

FOR Structure

  FOR Memory : nREG
    USE ENTITY work.nREG(Structure);
  END FOR;

  FOR Connect : AND2
    USE ENTITY work.AND2(Behavior);
  END FOR;

  FOR State : RSFFR
    USE ENTITY work.RSFFR(Behavior);
  END FOR;

  FOR Out0 : BUF
    USE ENTITY work.BUF(Behavior);
  END FOR;
 
  FOR Out1: BUF
    USE ENTITY work.BUF(Behavior);
  END FOR;  

  FOR Out2: BUF
    USE ENTITY work.BUF(Behavior);
  END FOR;  

END FOR; -- for structure
 
END FIFOstage_config;