--==========================================================
-- Design units : FiFoPackage
--
-- File name    : FIFOpack.vhd
--
-- Purpose      : Package for required elements of FiFo-Memory
--                including gates and their delay times
--
-- Limitations  : none
--
-- Library      : work
--
-- Dependencies : IEEE.std_logic_1164
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
-- V1.0    cjt    16.11.95       new
--===========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

PACKAGE FIFOpack IS

------------------------------------------------------------
-- Specification of a Buffer -------------------------------
------------------------------------------------------------

COMPONENT BUF
  PORT(X: IN std_logic;
       Y: OUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Specification of an AND2-Gate ---------------------------
------------------------------------------------------------

COMPONENT AND2
  PORT(A: IN std_logic;
       B: IN std_logic;
       Y: OUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Specification of a RS-FlipFlop with asyn-  --------------
-- chronous reset                             --------------
------------------------------------------------------------

COMPONENT RSFFR
  PORT(S : IN std_logic;
       R : IN std_logic;
       C : IN std_logic;
       Q : OUT std_logic;
       QZ: OUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Specification of a n-bit Register -----------------------
------------------------------------------------------------

COMPONENT nREG
  GENERIC(N: Positive);
  PORT(CLK: IN std_logic;
       S  : IN std_logic;
       X  : IN std_logic_vector(N-1 DOWNTO 0);
       Y  : OUT std_logic_vector(N-1 DOWNTO 0));
END COMPONENT;
								
------------------------------------------------------------
-- Specification of a D-FlipFlop ---------------------------
------------------------------------------------------------

COMPONENT DFF
  PORT (D  : IN std_logic;
	CLK: IN std_logic;
	Q  : OUT std_logic;
	QZ : OUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Specification of a FIFO Shift - Register ----------------
------------------------------------------------------------

COMPONENT FIFObehave
  GENERIC (N: Positive);
  PORT (DataIn     : IN INTEGER;
	ShiftIn    : IN std_logic;
	ShiftOut   : IN std_logic;
	MasterReset: IN std_logic;
	DataOut    : OUT INTEGER;
        MemoryFlag : INOUT std_logic_vector(N-1 DOWNTO 0);
	InputReady : INOUT std_logic;
	OutputReady: INOUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Implementation of a FIFO Shift - Register with ----------
-- asynchronous handshake ----------------------------------
------------------------------------------------------------

COMPONENT FIFOstruc
  GENERIC (M,N: Positive);
  PORT (DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
	ShiftIn    : IN std_logic;
	ShiftOut   : IN std_logic;
	MasterReset: IN std_logic;
	DataOut    : OUT std_logic_vector(M-1 DOWNTO 0);
	InputReady : OUT std_logic_vector;
	OutputReady: OUT std_logic_vector);
END COMPONENT;

------------------------------------------------------------
-- Structural Description of a single FIFO stage -----------
------------------------------------------------------------

COMPONENT FIFOstage
  GENERIC (M: Positive);
  PORT (DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
	ShiftIn    : IN std_logic;
	ShiftOut   : IN std_logic;
	MasterReset: IN std_logic;
	DataOut    : OUT std_logic_vector(M-1 DOWNTO 0);
	InputReady : OUT std_logic;
	ClockPulse : OUT std_logic;
	OutputReady: OUT std_logic);
END COMPONENT;

------------------------------------------------------------
-- Behavioral description of a stimuli generator ----------
------------------------------------------------------------

COMPONENT FIFOstim
  GENERIC (M: POSITIVE);
  PORT (DataInInt   : OUT INTEGER;
	DataIn      : OUT std_logic_vector(M-1 DOWNTO 0);
	ShiftIn     : OUT std_logic;
	ShiftOut    : OUT std_logic;
	MasterReset : OUT std_logic);

END COMPONENT;

END FIFOpack;

------------------------------------------------------------
-- Implementations of the required gates and registers ------
------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY BUF IS
  PORT (X: IN std_logic;
	Y: OUT std_logic);
END BUF;

ARCHITECTURE Behavior OF BUF IS
BEGIN
  p0: PROCESS(X)
  BEGIN
    Y<=transport X AFTER 2 Ns;
  END PROCESS;
END Behavior;

----------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY DFF IS
  PORT (D  : IN std_logic;
	CLK: IN std_logic;
	Q  : OUT std_logic;
	QZ : OUT std_logic);
END DFF;

ARCHITECTURE Behavior OF DFF IS
BEGIN
  p0 : PROCESS (CLK)
  BEGIN
    IF CLK='1' THEN
      Q <= TRANSPORT D AFTER 5 Ns;
    END IF;
  END PROCESS;
END Behavior;

----------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY AND2 IS
  PORT (A: IN std_logic;
	B: IN std_logic;
	Y: OUT std_logic);
END AND2;

ARCHITECTURE Behavior OF AND2 IS
BEGIN
  P0: PROCESS(A,B)
  BEGIN
    IF A='1'AND B='1' THEN 
	Y<=transport '1' AFTER 3 Ns;
      ELSE
	Y<=transport '0' AFTER 3 Ns;
    END IF;
  END PROCESS;
END Behavior;

----------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY RSFFR IS
  PORT (S : IN std_logic;
	R : IN std_logic;
	C : IN std_logic;
	QZ: OUT std_logic;
	Q : OUT std_logic);
	
END RSFFR;

ARCHITECTURE Behavior OF RSFFR IS
BEGIN

  p0: PROCESS (S,R,C)
    VARIABLE last_state: std_logic := '0';
  BEGIN
    IF C='1' THEN
      last_state := '0';
    ELSE
      IF S='0' AND R='0' 
	THEN last_state := last_state;
      elsIF S='0' AND R='1'
	THEN last_state := '0';
      elsIF S='1' AND R='0'
	THEN last_state := '1';
      ELSE
	last_state := '1';
      END IF;
    END IF;
    IF last_state = '1' THEN
       Q <= transport '1' AFTER 5 Ns;
      QZ <= transport '0' AFTER 5 Ns;
    ELSE
       Q <= transport '0' AFTER 5 Ns;
      QZ <= transport '1' AFTER 5 Ns;
    END IF;
  END PROCESS;
END Behavior;

----------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY nREG IS
  GENERIC(N: Positive);
  PORT(CLK: IN std_logic;
       S  : IN std_logic;
       X  : IN std_logic_vector (N-1 DOWNTO 0);
       Y  : OUT std_logic_vector (N-1 DOWNTO 0));
END nREG;

ARCHITECTURE Structure OF nREG IS

  SIGNAL internal: std_logic := '0';

  BEGIN
    G0: IF N > 0 GENERATE
      Unit0: AND2
	PORT MAP(CLK,S,internal);
    END GENERATE;

    G: FOR I IN 0 to N-1 GENERATE
    
    Unit1: DFF
      PORT MAP (X(I),internal,Y(I));
  END GENERATE;

END Structure;

CONFIGURATION nREG_config OF nREG IS
  FOR Structure
    FOR G0
      FOR Unit0: AND2
	USE ENTITY work.AND2(Behavior);
      END FOR;
    END FOR; -- G0
    FOR G
      FOR Unit1: DFF
	USE ENTITY work.DFF(Behavior);
      END FOR; 
    END FOR; -- G
  END FOR; -- Structure
END nREG_config;
---------------------------------------