--==========================================================
-- Design units : DIVtb (testbench)
--
-- File name    : DIVtb.vhd
--
-- Purpose      : Testbench for divider array
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : IEEE, DIVpack, DIVarray, DIVbehave, DIVstim
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    20.01.95       ESA standard
-- V1.0    hpe    03.04.95       comments
-- V2.0    cjt    09.09.95       external stimuli
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.DIVpack.ALL;

ENTITY DIVtb IS END DIVtb;

--============================ARCHITECTURE==================

ARCHITECTURE Testbench OF DIVtb IS

  CONSTANT M: Positive := 3;  -- bit length of divisor
  CONSTANT K: Positive := 6;  -- bit length of dividend

  SIGNAL N : Integer RANGE (2**K)-1 DOWNTO 0;     -- integer divisor
  SIGNAL D : Integer RANGE (2**M)-1 DOWNTO 0;     -- integer dividend
  SIGNAL Q : Integer RANGE (2**(K-M))-1 DOWNTO 0; -- integer quotient
  SIGNAL R : Integer RANGE (2**M)-1 DOWNTO 0;     -- integer remainder

  SIGNAL bin_N : std_logic_vector (K-1 DOWNTO 0);    -- binary divisor
  SIGNAL bin_D : std_logic_vector(M-1 DOWNTO 0);    -- binary dividend
  SIGNAL bin_Q : std_logic_vector((K-M)-1 DOWNTO 0);  -- binary quotient
  SIGNAL bin_R : std_logic_vector(M-1 DOWNTO 0);    -- binary remainder

  COMPONENT DIVarray
    GENERIC (M : Positive := 3;  -- bit length of divisor
             K : Positive := 6); -- bit length of dividend
    PORT (N : IN std_logic_vector(K-1 DOWNTO 0); -- dividend in
          D : IN std_logic_vector(M-1 DOWNTO 0); -- divisor in
          Q : INOUT std_logic_vector((K-M)-1 DOWNTO 0); -- quotient out
          R : OUT std_logic_vector(M-1 DOWNTO 0)); -- remainder out
  END COMPONENT;

  COMPONENT DIVbehave
    GENERIC(M : Positive := 3;  -- bit length of divisor
            K : Positive := 6); -- bit length of dividend
    PORT(N_in : IN  Integer RANGE (2**K)-1 DOWNTO 0;     -- dividend in
         D_in : IN  Integer RANGE (2**M)-1 DOWNTO 0;     -- divisor in
         Q_out : OUT Integer RANGE (2**(K-M))-1 DOWNTO 0; -- quotient out
         R_out : OUT Integer RANGE (2**M)-1 DOWNTO 0);    -- remainder out
  END COMPONENT;

  COMPONENT DIVstim
    GENERIC ( M : POSITIVE := 3;  -- bit lenght of divisor
              K : POSITIVE := 6); -- bit lenght of dividend
    PORT ( N_test :   OUT Integer RANGE (2**K)-1 DOWNTO 0; -- integer divisor
           D_test :   OUT Integer RANGE (2**M)-1 DOWNTO 0; -- integer dividend
           Nvec_test : OUT std_logic_vector((K-1) DOWNTO 0);  -- binary divisor
           Dvec_test : OUT std_logic_vector((M-1) DOWNTO 0)); -- binary dividend
  END COMPONENT;

BEGIN

  MUT : DIVarray          -- Description of model under test
    GENERIC MAP(M,K)
    PORT MAP(bin_N,bin_D,bin_Q,bin_R);

  SPEC : DIVbehave        -- Specification by behavioral description
    GENERIC MAP(M,K)
    PORT MAP(N,D,Q,R);
 
  STIM : DIVstim          -- Behavioral description of stimuli generator
    GENERIC MAP(M,K)
    PORT MAP(N,D, bin_N, bin_D );

END Testbench;

--============================CONFIGURATION=================

CONFIGURATION DIVtb_Config OF DIVtb IS
  FOR Testbench
    FOR MUT : DIVarray
      USE ENTITY work.DIVarray(Structure);
    END FOR;
    FOR SPEC : DIVbehave
      USE ENTITY work.DIVbehave(Behavior);
    END FOR;
    FOR STIM : DIVstim
      USE ENTITY work.DIVstim(Behavior);
    END FOR;
  END FOR;
END DIVtb_Config;