--==========================================================
-- Design units : DIVpack (package)
--
-- File name    : DIVpack.vhd
--
-- Purpose      : Summary of components for divider arrary
--                benchmark
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : IEEE
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    19.01.95       ESA standard
-- V2.0    cjt    23.09.95       Integration of stimuli generator
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE DIVpack IS

------------------------------------------------------------
-- specification of a division in vhdl 
------------------------------------------------------------

COMPONENT DIVbehave           -- N = Q*D + R
  GENERIC (M: Positive := 3;  -- bitlength of divisor
           K: Positive := 6); -- bit length of dividend
  PORT(N: IN  Integer RANGE 2**K-1 DOWNTO 0;     -- N input
       D: IN  Integer RANGE 2**M-1 DOWNTO 0;     -- D input
       Q: OUT Integer RANGE 2**(K-M)-1 DOWNTO 0; -- Q output
       R: OUT Integer RANGE 2**M-1 DOWNTO 0);    -- R output
END COMPONENT;

------------------------------------------------------------
-- stimuli generator
------------------------------------------------------------

COMPONENT DIVstim           
  GENERIC (M: Positive := 3;  -- bitlength of divisor
           K: Positive := 6); -- bit length of dividend
  PORT(N_test: OUT Integer RANGE 2**K-1 DOWNTO 0;     -- N input
       D_test: OUT Integer RANGE 2**M-1 DOWNTO 0;     -- D input
       Q_test: OUT std_logic_vector((K-1) DOWNTO 0); -- Q output
       R_test: OUT std_logic_vector((M-1) DOWNTO 0));    -- R output
END COMPONENT;

------------------------------------------------------------
-- structural description of a divider array with restoring
-- subtraction
------------------------------------------------------------

COMPONENT DIVarray           -- N = Q*D + R         
  GENERIC(M: Positive := 3;  -- bit length for divisor      
          K: Positive := 6); -- bit length dor dividend
  PORT(N:    IN std_logic_vector(K-1 DOWNTO 0);   -- N input
       D:    IN std_logic_vecTOr(M-1 DOWNTO 0);   -- D input
       Nvec: INOUT std_logic_vector(K-M-1 DOWNTO 0);  -- binary divisor
       Dvec: OUT std_logic_vector(M-1 DOWNTO 0)); -- binary dividend
END COMPONENT;

------------------------------------------------------------
-- the following components are needed for the structural 
-- description of the array
------------------------------------------------------------

COMPONENT DIVcell 
   PORT (DivIn: IN std_logic;      -- division bit in
         Rem1: IN std_logic;       -- remainder bit of dividend in
         BorrowIn: IN std_logic;   -- carry in
         SubIn: IN std_logic;      -- restore subtraction out
         BorrowOut: OUT std_logic; -- carry out
         SubOut: OUT std_logic;    -- restore subtraction out
         DivOut: OUT std_logic;    -- divisor out
         Dif: OUT std_logic);      -- difference out
END COMPONENT;

COMPONENT DIVOutput 
  PORT(A: IN std_logic;     -- data in
       B: IN std_logic;     -- data in
       Y: OUT std_logic;    -- data out
      nY: OUT std_logic);   -- data out
END COMPONENT;

END DIVpack;