--========================================================
-- Design units : REG_5_clr (Entity, Architecture)
--
-- File name    : REG_5_clr.vhd
--
-- Purpose      : 5 bit register with clear, load, reset
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : -
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    04.07.1996     new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY REG_5_clr IS
PORT(DataIn : IN std_logic_vector(4 DOWNTO 0);
     Clear  : IN std_logic;
     Load   : IN std_logic;
     Reset  : IN std_logic;                        -- Reset on active low
     Clk    : IN std_logic;
     DataOut: OUT std_logic_vector(4 DOWNTO 0));
END REG_5_clr;

--============================ARCHITECTURE==================

ARCHITECTURE Behavior OF REG_5_clr IS

BEGIN

  MAIN: PROCESS(Clk,Clear,Load,Reset,DataIn)

    BEGIN

      IF Reset = '0' THEN
         DataOut <= "00000";
      END IF;

      IF (Clk = '1' AND Clk'event) THEN

        IF Clear = '1' THEN
          DataOut <= "00000";
        END IF;

        IF Load = '1' THEN
          DataOut <= DataIn;
        END IF;

      END IF;

   END PROCESS;

END Behavior;