--==========================================================
-- Design units : BlackJack_Pack
--
-- File name    : BlackJack_Pack.vhd
--
-- Purpose      : Package for used elements of BJ dealer
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : -
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--
--=========================================================
library ieee;
use ieee.std_logic_1164.all;

PACKAGE BlackJack_Pack IS

COMPONENT MUX_four
PORT(A  : IN std_logic;   -- Data in Bit 0
     B  : IN std_logic;   -- Data in Bit 1
     C  : IN std_logic;   -- Data in Bit 2
     D  : IN std_logic;   -- Data in Bit 3
     S0 : IN std_logic;   -- Select input 0
     S1 : IN std_logic;   -- Select input 1
     Y  : OUT std_logic); -- Data out
END COMPONENT;

COMPONENT nMUX_four
GENERIC(N : POSITIVE := 4);
PORT(A  : IN std_logic_vector(N-1 DOWNTO 0);   -- Data in 0
     B  : IN std_logic_vector(N-1 DOWNTO 0);   -- Data in 1
     C  : IN std_logic_vector(N-1 DOWNTO 0);   -- Data in 2
     D  : IN std_logic_vector(N-1 DOWNTO 0);   -- Data in 3
     S0 : IN std_logic;   -- Select input 0
     S1 : IN std_logic;   -- Select input 1
     Y  : OUT std_logic_vector(N-1 DOWNTO 0)); -- Data out
END COMPONENT;

COMPONENT REG_5_clr
  PORT(DataIn : IN std_logic_vector(4 DOWNTO 0);
       Clear  : IN std_logic;
       Load   : IN std_logic;
       Reset  : IN std_logic;
       Clk    : IN std_logic;
       DataOut: OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;

COMPONENT BlackJack_CTRL
PORT (Card_rdy_s   : IN std_logic;   -- output of card ready button synchronize-ff
      Card_rdy_d   : IN std_logic;   -- output of card ready button delay-ff
      Acecard      : IN std_logic;   -- output of ace finder
      ScoreGT16    : IN std_logic;   -- output of score comparator
      ScoreGT21    : IN std_logic;   -- output of score comparator
      Stand        : IN std_logic;   -- output of STAND - FlipFlop
      Broke        : IN std_logic;   -- output of BROKE - FlipFlop
      Ace11flag    : IN std_logic;   -- output of ace = 11 flag
      Reset        : IN std_logic;   -- asynchronous reset active low
      Clk          : IN std_logic;   -- clock input
      Set_Stand    : OUT std_logic;  -- Set STAND - FlipFlop
      Clr_Stand    : OUT std_logic;  -- Clear STAND - FlipFlop
      Set_Broke    : OUT std_logic;  -- Set BROKE - FlipFlop
      Clr_Broke    : OUT std_logic;  -- Clear BROKE - FlipFlop
      Set_Ace11flag: OUT std_logic;  -- Set ace = 11 Flag
      Clr_Ace11flag: OUT std_logic;  -- Clear ace = 11 Flag
      Ld_Score     : OUT std_logic;  -- Load score to score register
      Clr_Score    : OUT std_logic;  -- Clear score register
      Adder_S0     : OUT std_logic;  -- select signal 0 for addselect mux
      Adder_S1     : OUT std_logic;  -- select signal 1 for addselect mux
      Hit          : OUT std_logic); -- indicate request for new card
END COMPONENT;

COMPONENT BlackJack_DataPath
PORT (Card         : IN std_logic_vector(3 DOWNTO 0); -- card value input
      Card_Ready   : IN std_logic;                    -- signal for valid card value
      Set_Ace11flag: IN std_logic;
      Clr_Ace11flag: IN std_logic;
      Ld_Score     : IN std_logic;
      Clr_Score    : IN std_logic;
      Set_Stand    : IN std_logic;
      Clr_Stand    : IN std_logic;
      Set_Broke    : IN std_logic;
      Clr_Broke    : IN std_logic;
      Adder_S0     : IN std_logic;                    -- select input 0 for seladd-mux
      Adder_S1     : IN std_logic;                    -- select input 1 for seladd-mux
      Reset        : IN std_logic;                    -- asynchronous reset active low
      Clk          : IN std_logic;                    -- Clock input
      Card_rdy_s   : OUT std_logic;                   -- synchronized card ready signal
      Card_rdy_d   : OUT std_logic;                   -- delayed card ready signal
      Acecard      : OUT std_logic;                   -- output of acefinder
      ScoreGT16    : OUT std_logic;                   -- output of score > 16 comparator
      ScoreGT21    : OUT std_logic;                   -- output of score > 21 comparator
      Stand        : OUT std_logic;                   -- output of STAND - FF
      Broke        : OUT std_logic;                   -- output of BROKE - FF
      Ace11flag    : OUT std_logic;                   -- output of Ace11flag - FF
      Score        : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;

COMPONENT BlackJack_BB
PORT(card_value : IN std_logic_vector(3 DOWNTO 0);
     card_ready : IN std_logic;
     clk        : IN std_logic;
     reset      : IN std_logic;
     stand_ind  : OUT std_logic;
     broke_ind  : OUT std_logic;
     hit_ind    : OUT std_logic;
     Score      : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;

COMPONENT BlackJack_Stim
PORT(Clk        : OUT std_logic;
     Reset      : OUT std_logic;
     Card_value : OUT std_logic_vector(3 DOWNTO 0);
     Card_int   : OUT positive;
     Card_ready : OUT std_logic);
END COMPONENT;

COMPONENT BlackJack_Behave
PORT(Card_Ready    : IN std_logic;
     Card_value    : IN integer;
     reset         : IN std_logic;
     clk           : IN std_logic;
     score         : INOUT integer := 0;
     stand         : OUT std_logic;
     broke         : OUT std_logic;
     hit           : INOUT std_logic);
END COMPONENT;

END BlackJack_Pack;