--==========================================================
-- Design units : BlackJack_CTRL (Entity,Archticture,Configuration)
--
-- File name    : BlackJack_CTRL.vhd
--
-- Purpose      : Generates control signals for bj datapath
--
-- Limitations  : -
--
-- Library      : work, IEEE
--
-- Dependencies : ELEMpack, GateLib, BlackJack_Pack, MUX_four
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    04.07.1996     new
--=========================================================

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.BlackJack_Pack.all;

ENTITY BlackJack_CTRL IS
PORT (Card_rdy_s   : IN std_logic;   -- output of card ready button synchronize-ff
      Card_rdy_d   : IN std_logic;   -- output of card ready button delay-ff
      Acecard      : IN std_logic;   -- output of ace finder
      ScoreGT16    : IN std_logic;   -- output of score comparator
      ScoreGT21    : IN std_logic;   -- output of score comparator
      Stand        : IN std_logic;   -- output of STAND - FlipFlop
      Broke        : IN std_logic;   -- output of BROKE - FlipFlop
      Ace11flag    : IN std_logic;   -- output of ace = 11 flag
      Reset        : IN std_logic;   -- asynchronous reset active low
      Clk          : IN std_logic;   -- clock input
      Set_Stand    : OUT std_logic;  -- Set STAND - FlipFlop
      Clr_Stand    : OUT std_logic;  -- Clear STAND - FlipFlop
      Set_Broke    : OUT std_logic;  -- Set BROKE - FlipFlop
      Clr_Broke    : OUT std_logic;  -- Clear BROKE - FlipFlop
      Set_Ace11flag: OUT std_logic;  -- Set ace = 11 Flag
      Clr_Ace11flag: OUT std_logic;  -- Clear ace = 11 Flag
      Ld_Score     : OUT std_logic;  -- Load score to score register
      Clr_Score    : OUT std_logic;  -- Clear score register
      Adder_S0     : OUT std_logic;  -- select signal 0 for addselect mux
      Adder_S1     : OUT std_logic;  -- select signal 1 for addselect mux
      Hit          : OUT std_logic); -- indicate request for new card
END BlackJack_CTRL;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF BlackJack_CTRL IS

SIGNAL StateA,StateB,nStateA,nStateB: std_logic;          -- State outputs of FlipFlops
SIGNAL S_Get,S_Add,S_Use,S_Test: std_logic;               -- State signals
SIGNAL nScoreGT16,nScoreGT21,nAce11flag: std_logic;       -- inverted signals
SIGNAL nCard_rdy_d, nCard_rdy_s: std_logic;               -- more inverted signals
SIGNAL Get_1,Get_2,Get_3,Test_1,Test_2,Test_3: std_logic; -- auxiliary 'states'
SIGNAL S_or_B,high: std_logic;                            -- auxiliary signals
SIGNAL MuxA0,MuxA1,MuxA2,MuxA3,MuxAout: std_logic;        -- input signals for multiplexer A
SIGNAL MuxB0,MuxB1,MuxB2,MuxB3,MuxBout: std_logic;        -- input signals for multiplexer B

BEGIN

high <= '1';

-- Invert some signals
Inv1: INV
  PORT MAP(Card_rdy_d,
           nCard_rdy_d);

Inv2: INV
  PORT MAP(ScoreGT21,
           nScoreGT21);

Inv3: INV
  PORT MAP(StateA,
           nStateA);

Inv4: INV
  PORT MAP(StateB,
           nStateB);

Inv5: INV
  PORT MAP(Ace11flag,
           nAce11flag);

Inv6: INV
  PORT MAP(Card_rdy_s,
           nCard_rdy_s);

-- State Outputs

State00: AND2
  PORT MAP(nStateA,
           nStateB,
           S_Get);

State01: AND2
  PORT MAP(StateA,
           nStateB,
           S_Add);

State10: AND2
  PORT MAP(nStateA,
           StateB,
           S_Use);

State11: AND2
  PORT MAP(StateA,
           StateB,
           S_Test);


-- Assign MUX Inputs

MuxB0 <= '0';
MuxB1 <= '1';
MuxB2 <= '1';
MuxB3 <= Test_3;

MuxA0 <= Get_2;

Gate0: NAND2  -- generate input for MaxA1
  PORT MAP(Acecard,
           nAce11flag,
           MuxA1);

MuxA2 <= '1';
MuxA3 <= Test_3;

-- Multiplexer for state encoding

MuxA: MUX_four
  PORT MAP(MuxA0,
           MuxA1,
           MuxA2,
           MuxA3,
           StateA,
           StateB,
           MuxAout);

MuxB: MUX_four
  PORT MAP(MuxB0,
           MuxB1,
           MuxB2,
           MuxB3,
           StateA,
           StateB,
           MuxBout);

-- State representing D-FFs with reset

FF_State_A: DFFsr
  PORT MAP(MuxAout,
           high,
           Reset,
           Clk,
           StateA);

FF_State_B: DFFsr
  PORT MAP(MuxBout,
           high,
           Reset,
           Clk,
           StateB);

-- Combinational logic

Gate1: AND2       -- Get_1
  PORT MAP(S_Get,
           nCard_rdy_s,
           Get_1);

Gate2: AND3       -- Get_2
  PORT MAP(S_Get,
           Card_rdy_s,
           nCard_rdy_d,
           Get_2);

Gate3: AND2       -- Get_3
  PORT MAP(Get_2,
           S_or_B,
           Get_3);

Gate4: AND3       -- Test_1
  PORT MAP(S_Test,
           ScoreGT16,
           nScoreGT21,
           Test_1);

Gate5: AND3       -- Test_2
  PORT MAP(S_Test,
           ScoreGT21,
           nAce11flag,
           Test_2);

Gate6: AND3       -- Test_3
  PORT MAP(S_Test,
           ScoreGT21,
           Ace11flag,
           Test_3);

Gate7: OR_2       -- S_or_B
  PORT MAP(Stand,
           Broke,
           S_or_B);

Gate8: OR_2
  PORT MAP(Get_3,
           Test_3,
           Clr_Ace11flag);

Gate9: OR_3
  PORT MAP(S_Add,
           S_Use,
           Test_3,
           Ld_Score);

-- Assign other output signals:

Hit <= Get_1;
Set_Stand <= Test_1;
Clr_Stand <= Get_2;
Set_Broke <= Test_2;
Clr_Broke <= Get_2;
Set_Ace11flag <= S_Use;
Adder_S1 <= S_Add;
Adder_S0 <= Test_3;
Clr_Score <= Get_3;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION BlackJack_CTRL_Config OF BlackJack_CTRL IS
FOR Structure

  FOR ALL : AND2
    USE ENTITY work.AND2(Behavior);
  END FOR;

  FOR ALL : AND3
    USE ENTITY work.AND3(Behavior);
  END FOR;

  FOR ALL : OR_2
    USE ENTITY work.OR_2(Behavior);
  END FOR;

  FOR ALL : OR_3
    USE ENTITY work.OR_3(Behavior);
  END FOR;

  FOR ALL : NAND2
    USE ENTITY work.NAND2(Behavior);
  END FOR;

  FOR ALL : MUX_four
    USE ENTITY work.MUX_four(Behavior);
  END FOR;

  FOR ALL : DFFsr
    USE ENTITY work.DFFsr(Behavior);
  END FOR;

  FOR ALL : INV
    USE ENTITY work.INV(Behavior);
  END FOR;

END FOR;
END BlackJack_CTRL_Config;