--==========================================================
-- Design units : AssocMemCirc
--                (entitiy, architecture and configuration)
--
-- File name    : AssocMemCirc.vhd
--
-- Purpose      : Circuit with Associative Memory 
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : AssocMemCtrl, AssocMemArray
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95       new
-- V2.0    cjt    18.10.95       ESA-Standard, reset on active low
--===========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.AssocMempack.all;

ENTITY AssocMemCirc IS
  GENERIC (M: Positive := 4;
           N: Positive := 4);
  PORT (DataIn:       IN std_logic_vector(M-1 DOWNTO 0);     
        MaskIn:       IN std_logic_vector(M-1 DOWNTO 0);     
        AddressIn:    IN std_logic_vector(N-1 DOWNTO 0);     
        Store:        IN std_logic;                          
        SelectAdrMat: IN std_logic;                          
        Clock:        IN std_logic;                          
        WriteEnable:  IN std_logic;                          
        Reset:        IN std_logic;                          -- reset on active low
        End1:         OUT std_logic;                         
        DataOut:      OUT std_logic_vector(M-1 DOWNTO 0));   
END AssocMemCirc;

--==========================ARCHITECTURE=====================

ARCHITECTURE Structure OF AssocMemCirc IS
  SIGNAL Data_word,Data_out,Mask_word: std_logic_vector(M-1 DOWNTO 0);
  SIGNAL Match,Select_word,Address_word,Prior: std_logic_vector(N-1 DOWNTO 0);
  SIGNAL StoreRes: std_logic := '0';
BEGIN

  Data_Register : nREG
    GENERIC MAP (M)
    PORT MAP (Clock,
              Store,
              DataIn,
              Data_word);

  Mask_Register : nREG
    GENERIC MAP (M)
    PORT MAP (Clock,
              Store,
              MaskIn,
              Mask_word);

  Memory : AssocMemArray
    GENERIC MAP (M,N)
    PORT MAP (WriteEnable,
              Data_word,
              Mask_word,
              Select_word,
              Data_out,
              Match);

  DataOut_Register : nREG
    GENERIC MAP (M)
    PORT MAP (Clock,
              StoreRes,
              Data_out,
              DataOut);

  Check : priority
    GENERIC MAP (N)
    PORT MAP (Match,
              Prior);

  Select_Control : nMUX
    GENERIC MAP (N)
    PORT MAP (Address_word,
              Prior,
              SelectAdrMat,
              Select_word);

  Address_Register : nREG
    GENERIC MAP (N)
    PORT MAP (Clock,
              Store,
              AddressIn,
              Address_word);

  End_Flag : BUF
    PORT MAP (StoreRes,
              End1);

  Controller : AssocMemCtrl
    PORT MAP (Store,
              SelectAdrMat,
              WriteEnable,
              Reset,
              StoreRes);

END Structure;

--==========================CONFIGURATION====================

CONFIGURATION AssocMemCircConfig OF AssocMemCirc IS

  FOR Structure
 
    FOR ALL : nREG
      USE ENTITY work.nREG(Structure);
    END FOR;
 
    FOR Memory : AssocMemArray
      USE ENTITY work.AssocMemArray(Structure);
    END FOR;

    FOR Check : priority 
      USE ENTITY work.priority(Structure);
    END FOR;
 
    FOR Select_Control : nMUX 
      USE ENTITY work.nMUX(Structure);
    END FOR;

    FOR End_Flag : BUF
      USE ENTITY work.BUF(Behavior);
    END FOR;

    FOR Controller : AssocMemCtrl
      USE ENTITY work.AssocMemCtrl(Structure);
    END FOR;
 
  END FOR;

END AssocMemCircConfig;