--========================================================== -- Design units : AssocMemCell -- (entitiy, architecture and configuration) -- -- File name : AssocMemCell.vhd -- -- Purpose : One Cell for Associative Memory -- -- Limitations : None -- -- Library : WORK -- -- Dependencies : None -- -- Author : Hans-Peter Eich, REFT -- -- Simulator : Synopsys V3.1a on SUN SPARCstation 10 -- ------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- V1.0 hpe 02.04.95 new -- V2.0 cjt 18.10.95 ESA-Standard --=========================================================== LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.ELEMpack.all; ENTITY AssocMemCell IS PORT (WriteEnable : IN std_logic; -- Enable signal DataIn : IN std_logic; -- Input data bit Mask : IN std_logic; -- Input mask bit Sel : IN std_logic; -- Input select bit Match : OUT std_logic; -- Output match bit DataOut : OUT std_logic);-- Output data bit END AssocMemCell; --==========================ARCHITECTURE===================== ARCHITECTURE Structure OF AssocMemCell IS SIGNAL I1_out,I2_out,I3_out,I4_out: std_logic := '0'; BEGIN I1 : INV PORT MAP (Mask,I1_out); I2 : AND3 PORT MAP (WriteEnable,I1_out,Sel,I2_out); I3 : DFF PORT MAP (DataIn,I2_out,I3_out); I4 : NXOR2 PORT MAP (DataIn,I3_out,I4_out); I5 : AND2 PORT MAP (I1_out,I4_out,Match); I6 : AND2 PORT MAP (I3_out,Sel,DataOut); END Structure; --==========================CONFIGURATION==================== CONFIGURATION AssocMemCellConfig OF AssocMemCell IS FOR Structure FOR I1 : INV USE ENTITY work.inv(Behavior); END FOR; FOR I2 : AND3 USE ENTITY work.and3(Behavior); END FOR; FOR I3 : DFF USE ENTITY work.dff(Behavior); END FOR; FOR I4 : NXOR2 USE ENTITY work.nxor2(Behavior); END FOR; FOR ALL : AND2 USE ENTITY work.and2(Behavior); END FOR; END FOR; END AssocMemCellConfig;