--==========================================================
-- Design units : Carry_Lookahead_Adder(entity,architecture,configuration)
--
-- File name    : CLA_N-Bit_Adder.vhd
--
-- Purpose      : N-Bit adder with carry lookahead
--
-- Limitations  : n should be divisible by 4
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack, Bit_Add_G_P, Carry_Generator,Four_bit_Adder
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    19.12.95       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.CarryLookaheadPackage.all;

ENTITY Carry_Lookahead_Adder IS
  GENERIC(M: POSITIVE := 8);
  PORT(DataIn_A: IN  std_logic_vector(M-1 DOWNTO 0);
       DataIn_B: IN  std_logic_vector(M-1 DOWNTO 0);
       CarryIn : IN  std_logic;
       DataOut : OUT std_logic_vector(M-1 DOWNTO 0);
       CarryOut: OUT std_logic);
END Carry_Lookahead_Adder;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Carry_Lookahead_Adder IS

CONSTANT N :INTEGER  := M/4-(M MOD 4)/4;    -- N internal blocks are needed
CONSTANT R :INTEGER := M-N*4;      -- Remaining input lines for last block

SIGNAL internal : std_logic_vector(N+1 DOWNTO 0);
SIGNAL a_int,b_int,s_int: std_logic_vector(3 DOWNTO 0);

BEGIN 

  internal(0) <= CarryIn;

  Loop1: FOR i IN 0 TO N-1 GENERATE
    Adder_Stage: Four_bit_Adder
      PORT MAP(DataIn_A((i+1)*4-1 DOWNTO i*4),
               DataIn_B((i+1)*4-1 DOWNTO i*4),
               internal(i),
               DataOut((i+1)*4-1 DOWNTO i*4),
               open,
               open,
               internal(i+1));
  END GENERATE;

  CarryOut <= internal(N);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Carry_Lookahead_Adder_Config OF Carry_Lookahead_Adder IS

  FOR Structure

    FOR Loop1

      FOR Adder_Stage: Four_bit_Adder
        USE ENTITY work.Four_bit_adder(Structure);
      END FOR;

    END FOR;

  END FOR;

END Carry_Lookahead_Adder_Config;