--==========================================================
-- Design units : Carry_Generator(entity, architecture, configuration)
--
-- File name    : CLA_CarryGen.vhd
--
-- Purpose      : Generates Block Carry,- generate, -propagate
--
-- Limitations  : 4 bit
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- v1.0    cjt    19.12.95       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.CarryLookaheadPackage.all;

ENTITY Carry_Generator IS
  PORT(gen          : IN std_logic_vector(3 DOWNTO 0);    -- Generate input
       propagate    : IN std_logic_vector(3 DOWNTO 0);    -- Propagate input
       CarryIn      : IN std_logic;                   -- Carry input
       CarryOut     : OUT std_logic_vector(2 DOWNTO 0);   -- Carry output
       B_Carry      : OUT std_logic;                  -- Block carry output
       B_Propagate  : OUT std_logic;                  -- Block carry propagate output
       B_Generate   : OUT std_logic);                 -- Block carry generate output
END Carry_Generator;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Carry_Generator IS

  SIGNAL int_carry : std_logic_vector(3 DOWNTO 0);
  SIGNAL internal : std_logic_vector(9 DOWNTO 0);
  SIGNAL temp_BCG, temp_BCP : std_logic;

  BEGIN

    int_carry(0) <= CarryIn;

    unit0: AND2
      PORT MAP(int_carry(0),
               propagate(0),
               internal(0));

    unit1: AND3
      PORT MAP(int_carry(0),
               propagate(0),
               propagate(1),
               internal(1));

    unit2: AND2
      PORT MAP(gen(0),
               propagate(1),
               internal(2));

    unit3: AND4
      PORT MAP(int_carry(0),
               propagate(0),
               propagate(1),
               propagate(2),
               internal(3));

    unit4: AND3
      PORT MAP(gen(0),
               propagate(1),
               propagate(2),
               internal(4));

    unit5: AND2
      PORT MAP(gen(1),
               propagate(2),
               internal(5));

    unit6: AND4
      PORT MAP(gen(0),
               propagate(1),
               propagate(2),
               propagate(3),
               internal(6));

    unit7: AND3
      PORT MAP(gen(1),
               propagate(2),
               propagate(3),
               internal(7));

    unit8: AND2
      PORT MAP(gen(2),
               propagate(3),
               internal(8));

    unit9: OR_4
      PORT MAP(gen(3),
               internal(8),
               internal(7),
               internal(6),
               temp_BCG);

    unit10: AND4
      PORT MAP(propagate(0),
               propagate(1),
               propagate(2),
               propagate(3),
               temp_BCP);

    unit11: OR_4
      PORT MAP(gen(2),
               internal(5),
               internal(4),
               internal(3),
               int_carry(3));

    unit12: OR_3
      PORT MAP(gen(1),
               internal(2),
               internal(1),
               int_carry(2));

    unit13: OR_2
      PORT MAP(gen(0),
               internal(0),
               int_carry(1));

    unit14: AND2
      PORT MAP(temp_BCP,
               int_carry(0),
               internal(9));

    unit15: OR_2
      PORT MAP(internal(9),
               temp_BCG,
               B_Carry);

    B_Propagate <= temp_BCP;
    B_Generate  <= temp_BCG;

    CarryOut(0) <= int_carry(1);
    CarryOut(1) <= int_carry(2);
    CarryOut(2) <= int_carry(3);


END Structure;

--============================CONFIGURATION=================

CONFIGURATION Carry_Generator_Config OF Carry_Generator IS

  FOR Structure

    FOR all: AND2
      USE ENTITY work.AND2(Behavior);
    END FOR;

    FOR all: AND3
      USE ENTITY work.AND3(Behavior);
    END FOR;

    FOR all: AND4
      USE ENTITY work.AND4(Behavior);
    END FOR;

    FOR all: OR_2
      USE ENTITY work.OR_2(Behavior);
    END FOR;

    FOR all: OR_3
      USE ENTITY work.OR_3(Behavior);
    END FOR;

    FOR all: OR_4
      USE ENTITY work.OR_4(Behavior);
    END FOR;

  END FOR;

END Carry_Generator_Config;