--==========================================================
-- Design units : Four_bit_Adder(entity,architecture,configuration)
--
-- File name    : CLA_4_Bit_Adder.vhd
--
-- Purpose      : Adds 4 bit numbers with carry lookahead technique
--
-- Limitations  : 4 bit
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack, Bit_Add_G_P, Carry_Generator
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- v1.0    cjt    19.12.95       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.CarryLookaheadPackage.all;

ENTITY Four_bit_Adder IS
  PORT(A_In  : IN std_logic_vector(3 DOWNTO 0);   -- First summand
       B_In  : IN std_logic_vector(3 DOWNTO 0);   -- Second summand
       C_In  : IN std_logic;                  -- Carry IN
       S_Out : OUT std_logic_vector(3 DOWNTO 0);  -- Sum OUT
       BP_Out: OUT std_logic;                 -- Block carry propagate OUT
       BG_Out: OUT std_logic;                 -- Block carry GENERATE OUT
       BC_Out: OUT std_logic);                -- Block carry OUT
END Four_bit_Adder;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Four_bit_Adder IS

  SIGNAL carry : std_logic_vector(3 DOWNTO 0);
  SIGNAL propagate,gen: std_logic_vector(3 DOWNTO 0);

  BEGIN

  carry(0) <= C_In;

  Loop1: FOR i IN 0 TO 3 GENERATE
    Adder_Stage: Bit_Add_G_P
    PORT MAP(A_In(i),               -- First summand
             B_In(i),               -- Second summand
             carry(i),              -- Carry in
             S_Out(i),              -- Sum out
             gen(i),                -- Carry generate out
             propagate(i));         -- Carry propagate out
    END GENERATE;

  Lookahead: Carry_Generator
    PORT MAP(gen,                   -- Generate input
             propagate,             -- Propagate input
             carry(0),              -- Carry input
             carry(3 DOWNTO 1),     -- Carrry output
             BC_Out,                -- Block carry output
             BP_Out,                -- Block carry propagate output
             BG_Out);               -- Block carry generate output

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Four_bit_Adder_Config OF Four_bit_Adder IS

  FOR Structure
Bit_Add_G_P
    FOR Loop1

      FOR Adder_Stage: Bit_Add_G_P
        USE ENTITY work.bit_add_g_p(Structure);
      END FOR;

    END FOR;  -- Loop1

    FOR Lookahead: Carry_Generator
      USE ENTITY work.carry_generator(Structure);
    END FOR;

  END FOR;

END Four_bit_Adder_Config;