--==========================================================
-- Design units : MATRIXtestbench
--                (entity, architecture and configuration)
--
-- File name    : MATRIXtestbench.vhd
--
-- Purpose      : testbench for 2 dim systolic array
--
-- Limitations  : none
--
-- Library      : WORK
--
-- Dependencies : IEEE, MATRIXstim, MATRIXstruc, MATRIXbehave
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    cjt    08.08.95       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.MATRIXpack.ALL;
USE work.ELEMpack.ALL;

ENTITY MATRIXtestbench IS
END MATRIXtestbench;


--============================ARCHITECTURE==================

ARCHITECTURE Structure OF MATRIXtestbench IS
    CONSTANT M : Positive := 4;
    CONSTANT N : Positive := 8;
    CONSTANT E : Positive := 4;

SIGNAL MatrixA,MatrixB : std_logic_vector((E*M)-1 DOWNTO 0);
SIGNAL MatrixP         : std_logic_vector(((2*E-1)*N)-1 DOWNTO 0);
SIGNAL A,B,P           : INT_vector(E*E-1 DOWNTO 0);
SIGNAL reset, clk      : std_logic;

COMPONENT MATRIXstim
    GENERIC (M : Positive := 4;
             N : Positive := 8;
             E : Positive := 4);
    PORT (StrA    : OUT  std_logic_vector((E*M)-1 DOWNTO 0); -- data stream matrix A 
          StrB    : OUT  std_logic_vector((E*M)-1 DOWNTO 0); -- data stream matrix B
          reset   : OUT  std_logic;  -- asynchronuous reset on active low
          clk     : OUT  std_logic; -- clock out
          A       : OUT INT_vector(E*E-1 DOWNTO 0); -- integer stream matrix A
          B       : OUT INT_vector(E*E-1 DOWNTO 0)); -- integer stream matrix B
 
  END COMPONENT;

  COMPONENT MATRIXstruc
  GENERIC (M : POSITIVE := 4;
           N : POSITIVE := 8;
           E : POSITIVE := 4);
  PORT (StrAIn  : IN  std_logic_vector((E*M)-1 DOWNTO 0); -- stream in matrix A 
        StrBIn  : IN  std_logic_vector((E*M)-1 DOWNTO 0); -- stream in matrix B
        Reset_N : IN  std_logic; -- asynchronuous reset on active low
        clock   : IN  std_logic; -- clock input
        StrCOut : OUT std_logic_vector(((2*E-1)*N)-1 DOWNTO 0)); -- stream out matrix C
   
  END COMPONENT;

  COMPONENT MATRIXbehave
  GENERIC (E: POSITIVE := 4);
  PORT(A : IN  INT_vector (E*E-1 DOWNTO 0); -- Input Matrix A
       B : IN  INT_vector (E*E-1 DOWNTO 0); -- Input Matrix B
       P : OUT INT_vector (E*E-1 DOWNTO 0));-- Output Matrix P

  END COMPONENT;

BEGIN

  Stimuli   : MATRIXstim    -- Stimuli pattern description
                PORT MAP (MatrixA,MatrixB,reset,clk,A,B);

  MUT       : MATRIXstruc   -- Structural description of model under test
                PORT MAP (MatrixA,MatrixB,reset,clk,MatrixP);

  SPEC      : MATRIXbehave  -- Specification as behavioral description
                PORT MAP (A,B,P);

END Structure;


--============================CONFIGURATION=================

CONFIGURATION MATRIXtestbench_Config OF MATRIXtestbench IS

  FOR Structure

    FOR Stimuli : MATRIXstim
      USE ENTITY work.MATRIXstim(Behavior);
    END FOR;

    FOR MUT : MATRIXstruc
      USE ENTITY work.MATRIXstruc(Structure);
    END FOR;

    FOR SPEC : MATRIXbehave
      USE ENTITY work.MATRIXbehave(Behavior);
    END FOR;


  END FOR;

END MATRIXtestbench_Config;