--==========================================================
-- Design units : MATRIXpack (package)
--
-- File name    : MATRIXpack.vhd 
--
-- Purpose      : package for 2 dim systolic array
--
-- Limitations  : N = 2*M
--
-- Library      : WORK
--
-- Dependencies : IEEE,ELEMpack,multiplier benchmark
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    13.02.95       ESA standard
-- V1.0    hpe    03.04.95       one dimensional arrays
-- V2.0    cjt    31.08.95       1-dim complete, new struc-
--                               tural description
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE MATRIXpack IS
------------------------------------------------------------
-- Declaration of matrix type
------------------------------------------------------------

TYPE INT_vector IS ARRAY (Natural range <>) OF NATURAL;

------------------------------------------------------------
-- Specification of a matrix  multiplication
------------------------------------------------------------

COMPONENT MATRIXbehave
  GENERIC(M : Positive := 4;  -- bit length of input vector 
          N : Positive := 8;  -- bit length of output vector
          E : Positive := 4); -- E*E matrix elements
  PORT(A:  IN INT_vector (E*E-1 DOWNTO 0);  -- Input Matrix A
       B:  IN INT_vector (E*E-1 DOWNTO 0);  -- Input Matrix B
       P: OUT INT_vector (E*E-1 DOWNTO 0));  -- Output Matrix P
END COMPONENT;

------------------------------------------------------------
-- Structural description of a systolic array
------------------------------------------------------------

COMPONENT MATRIXstruc
  GENERIC(M : Positive := 4;  -- bit length of input vector
          N : Positive := 8;  -- bit length of output vector
          E : Positive := 4); -- number of matrix elements per row
  PORT(StrAIn  : IN  std_logic_vector((E*M)-1 DOWNTO 0); -- stream in matrix A 
       StrBIn  : IN  std_logic_vector((E*M)-1 DOWNTO 0); -- stream in matrix B
       Reset_N : IN  std_logic; -- asynchronuous reset on active low
       clock   : IN  std_logic; -- clock input
       StrCOut : OUT std_logic_vector(((2*E-1)*N)-1 DOWNTO 0)); -- stream out matrix C
END COMPONENT;

------------------------------------------------------------
-- The following components are needed for the structural 
-- description
------------------------------------------------------------

COMPONENT MATRIXcell
  GENERIC (M : Positive := 4;  -- bit length default m = 4
           N : Positive := 8); -- bit length default n = 8
  PORT(A_In    : IN std_logic_vector(M-1 DOWNTO 0); -- A stream in
       B_In    : IN std_logic_vector(M-1 DOWNTO 0); -- B stream in
       C_In    : IN std_logic_vector(N-1 DOWNTO 0); -- C stream in
       Reset_N : IN std_logic; -- asynchronuous reset on active low
       clock   : IN std_logic; -- clock input
       A_Out   : OUT std_logic_vector(M-1 DOWNTO 0);  -- A stream out
       B_Out   : OUT std_logic_vector(M-1 DOWNTO 0);  -- B stream out
       C_Out   : OUT std_logic_vector(N-1 DOWNTO 0)); -- C stream out
END COMPONENT;

COMPONENT MULTstruc
  GENERIC(N : Positive := 4);                       -- bit length default n = 4
  PORT(A : IN  std_logic_vector(N-1 DOWNTO 0);      -- N bit vector input
       B : IN  std_logic_vector(N-1 DOWNTO 0);      -- N bit vector input
       P : OUT std_logic_vector((2*N)-1 DOWNTO 0)); -- 2 * N bit vector output
END COMPONENT;

END MATRIXpack;