--==========================================================
-- Design units : FILTERstruc
--                (entity, architecture and configuration)
--
-- File name    : FILTERstruc.vhd
--
-- Purpose      : systolic filter
--
-- Limitations  : generic values should be n >= 2 * m
--
-- Library      : WORK
--
-- Dependencies : IEEE, FILTERpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUM SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    18.01.95       ESA standard
-- V1.1    cjt    06.07.95       Change to OR_2
--=========================================================
-- Note: This circuit requires a Multiplier circuit, e.g.
--       the one published with these benchmark circuits.
--       A makefile for correct analyzation and translation
--       for the SYSNOPSYS simulating environment and a short
--       script for the correct analyzation within SYNOPSYS
--       Design Analyzer are provided in this directory. Please
--       care that Design Analyzer is started from the directory
--       where FILTER and MULT are.
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.FILTERpack.ALL;

ENTITY FILTERstruc IS
  GENERIC(N: Positive := 12;   -- n bit output stream
          M: Positive := 4;    -- m bit input stream
          K: Positive := 3);   -- number of stages
  PORT (StreamIn: IN std_logic_vector(M-1 DOWNTO 0); -- input stream
        SelectWgtStr: IN std_logic;  -- select weight stream
        StoreWgt: IN std_logic;      -- store weigth
        StoreStr: IN std_logic;      -- store stream
        StoreRes: IN std_logic;      -- store result
        clk1: IN std_logic;          -- clock 1 in
        clk2: IN std_logic;          -- clock 2 in
        Reset_N: IN std_logic;       -- asynchronous reset active low
        ResultOut: OUT std_logic_vector(N-1 DOWNTO 0)); -- result stream out
END FILTERstruc;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF FILTERstruc IS

 SIGNAL zero: std_logic_vector(N-1 DOWNTO 0);

 TYPE temp_stream IS ARRAY(Natural RANGE <>) OF std_logic_vector(M-1 DOWNTO 0);
 TYPE temp_result IS ARRAY(Natural RANGE <>) OF std_logic_vector(N-1 DOWNTO 0);

 SIGNAL Stream: temp_stream(K DOWNTO 0);
 SIGNAL Result: temp_result(K DOWNTO 0);

BEGIN

  filter : FOR i IN 0 TO K-1 GENERATE
    stage : FILTERstage
    GENERIC MAP(N,M)
    PORT MAP(StreamIn => Stream(i),
             ResultIn => Result(i+1),
             SelectWgtStr => SelectWgtStr,
             StoreWgt => StoreWgt,
             StoreStr => StoreStr,
             StoreRes => StoreRes,
             clk1 => clk1,
             clk2 => clk2,
             Reset_N => Reset_N,
             StreamOut => Stream(i+1),
             ResultOut => Result(i));
    END GENERATE;

    Stream(0) <= StreamIn;
    ResultOut <= Result(0);

    init : FOR j IN 0 TO N-1 GENERATE
      zero(j) <= '0';
    END GENERATE;

    Result(K) <= zero;

END Structure; 

--============================CONFIGURATION=================

CONFIGURATION FILTERstruc_Config OF FILTERstruc IS
  FOR Structure
    FOR filter
      FOR stage : FILTERstage
        USE ENTITY work.FILTERstage(Structure);
      END FOR;
    END FOR;
  END FOR;
END FILTERstruc_Config;