--==========================================================
-- Design units : FILTERstage 
--                (entity, architecture and configuration)
--
-- File name    : FILTERstage.vhd
--
-- Purpose      : Stage for systolic filter benchmark
--
-- Limitations  : m bit input and weigth stream, n bit
--                output stream
--
--                NOTE : n should be choosen at least 2*m
--
-- Library      : WORK
--
-- Dependencies : IEEE, ELEMpack, FILTERpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on Sun SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    17.01.95       ESA standard
-- V1.1    cjt    03.05.95  
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.ELEMpack.ALL;
USE work.FILTERpack.ALL;

ENTITY FILTERstage IS
  GENERIC (N: Positive := 12;                        -- n bit result stream
           M: Positive := 4);                        -- m bit input stream
  PORT (StreamIn: IN std_logic_vector(M-1 DOWNTO 0); -- m bit data in
        ResultIn: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
        SelectWgtStr : IN std_logic;  -- select weigth or stream
        StoreWgt : IN std_logic;      -- store weight
        StoreStr: IN std_logic;       -- store stream
        StoreRes: IN std_logic;       -- store result 
        clk1: IN std_logic;           -- clock in
        clk2: IN std_logic;           -- clock2 in
        Reset_N: IN std_logic;        -- asynchronous reset active low
        StreamOut: OUT std_logic_vector(M-1 DOWNTO 0);  -- m bit stream out
        ResultOut: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit result out
END FILTERstage;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF FILTERstage IS
  SIGNAL Dpath0,Dpath1,Dpath2,Dpath6: std_logic_vector(M-1 DOWNTO 0);
  SIGNAL Dpath3,Dpath4: std_logic_vector((2*M)-1 DOWNTO 0);
  SIGNAL Dpath5: std_logic_vector(N-1 DOWNTO 0);
  SIGNAL zero: std_logic;
BEGIN

  zero <= '0';

  nDMUX_structure: nDMUX
    GENERIC MAP(M)
    PORT MAP(X => StreamIn,
             S => SelectWgtStr,
            Y0 => Dpath0,
            Y1 => Dpath1);

  Weight_register: nREGr
    GENERIC MAP(M)
    PORT MAP(CLK => clk1,
               S => StoreWgt,
               R => Reset_N,
               X => Dpath0,
               Y => Dpath2);

  Inputstream_register: nREGr
    GENERIC MAP(M)
    PORT MAP(CLK => clk1,
               S => StoreStr,
               R => Reset_N,
               X => Dpath1,
               Y => Dpath6);

  Multiplier: MULTstruc -- multiplier network benchmark
    GENERIC MAP(M)
    PORT MAP(A => Dpath2,
             B => Dpath6,
             P => Dpath3);

  Result_register: nREGr
    GENERIC MAP(2*M)
    PORT MAP(CLK => clk2,
               S => StoreRes,
               R => Reset_N,
               X => Dpath3,
               Y => Dpath4);

  Resultstream_register: nREGr
    GENERIC MAP(N)
    PORT MAP(CLK => clk2,
               S => StoreRes,
               R => Reset_N,
               X => ResultIn,
               Y => Dpath5);

  Adder: FILTERcra
    GENERIC MAP(N,2*M)
    PORT MAP(A => Dpath5,
             B => Dpath4,
             S => ResultOut);
  
  StreamOut <= Dpath6;

END Structure;

--============================CONFIGURATION=================
  
CONFIGURATION FILTERstage_Config OF FILTERstage IS
  FOR Structure
    FOR nDMUX_structure : nDMUX
      USE ENTITY work.nDMUX(Structure);
    END FOR; 
    FOR Weight_register : nREGr
      USE ENTITY work.nREGr(Structure);
    END FOR;
    FOR Inputstream_register : nREGr
      USE ENTITY work.nREGr(Structure);
    END FOR;
    FOR Multiplier : MULTstruc
      USE ENTITY work.MULTstruc(Structure);
    END FOR;
    FOR Result_register : nREGr
      USE ENTITY work.nREGr(Structure);
    END FOR;
    FOR Resultstream_register : nREGr
      USE ENTITY work.nREGr(Structure);
    END FOR;
    FOR Adder : FILTERcra
      USE ENTITY work.FILTERcra(Structure);
    END FOR;
  END FOR;
END FILTERstage_Config;