--==========================================================
-- Design units : FILTERcra
--                (entity,architecture and configuration)
--
-- File name    : FILTERcra.vhd
--
-- Purpose      : carry ripple adder for systolic filter
--
-- Limitations  : Result has a bit vector of length n
--                Input has length of m or n bit
--
-- Library      : WORK
--
-- Dependencies : IEEE, ELEMpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on Sun SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    17.01.95       ESA-Standard
-- V1.1    cjt    03.07.95       
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.ELEMpack.ALL;

ENTITY FILTERcra IS
  GENERIC(N: Positive := 12;                   -- default n = 12
          M: Positive := 4);                   -- default n = 4
  PORT(A: IN  std_logic_vector(N-1 DOWNTO 0);  -- n bit data in
       B: IN  std_logic_vector(M-1 DOWNTO 0);  -- m bit data out
       S: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit sum out 
END FILTERcra;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF FILTERcra IS
  SIGNAL temp: std_logic_vector(N-1 DOWNTO 0);
  SIGNAL zero: std_logic;
BEGIN

  zero <= '0';

  expand_structure : expand
    GENERIC MAP(M,N)
    PORT MAP (X => B,
              Y => temp);

  carry_ripple_adder : CRA
    GENERIC MAP(N)
    PORT MAP(A => A,
             B => temp,
           Cin => zero,
           Sum => S,
          Cout => OPEN);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION FILTERcra_Config OF FILTERcra IS
  FOR Structure
    FOR expand_structure : expand
      USE ENTITY work.expand(Structure);
    END FOR;
    FOR carry_ripple_adder : CRA
      USE ENTITY work.CRA(Structure);
    END FOR;
  END FOR;
END FILTERcra_Config;