--==========================================================
-- Design units : StopWatchReduce (Entity,Architecture,Configuration)
--
-- File name    : StopWatchReduce.vhd
--
-- Purpose      : Divides a clock signal by 10000
--
-- Limitations  : none
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    18.01.96       new
--=========================================================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.Stoppack.all;

ENTITY StopWatchReduce IS
PORT(Clk_in : IN  std_logic;
     Enable : IN  std_logic;
     Reset  : IN  std_logic;
     Clk_out: OUT std_logic);
END StopWatchReduce;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF StopWatchReduce IS

SIGNAL int : std_logic_vector(5 DOWNTO 0);
SIGNAL one,not_Enable : std_logic;

BEGIN

one <= '1';

Loop1: FOR i IN 0 TO 4 GENERATE
  Counter: Mod_10_Counter
    PORT MAP(one,Enable,int(i),open,int(i+1));
END GENERATE;

int(0) <= Clk_IN;

Gate1: AND2
PORT MAP(Enable,int(5),Clk_Out);


END Structure;

--============================CONFIGURATION=================

CONFIGURATION StopWatchReduce_Config OF StopWatchReduce IS
  FOR Structure
    FOR Loop1
      FOR ALL : Mod_10_Counter
        USE ENTITY work.mod_10_counter(Structure);
      END FOR;
    END FOR;
    FOR Gate1: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;
  END FOR;
END StopWatchReduce_Config;