--==========================================================
-- Design units : StopWatchPackage 
--
-- File name    : StopWatchPackage.vhd
--
-- Purpose      : Required elements for StopWatch
--
-- Limitations  : none
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    18.01.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;

PACKAGE Stoppack IS

COMPONENT Pulse_Generator
  PORT(Clk : OUT std_logic := '0');
END COMPONENT;

COMPONENT Display_Unit
  PORT(Data  : IN  std_logic_vector(3 DOWNTO 0);
       Output: OUT std_logic_vector(6 DOWNTO 0));
END COMPONENT;

COMPONENT Mod_6_Counter
  PORT(Enable : IN std_logic;   -- Enable counter input
       Reset  : IN std_logic;   -- Reset on active low
       Clk    : IN std_logic;   -- Clock input
       DataOut: OUT std_logic_vector(2 DOWNTO 0);  -- 3 bits data OUT
       Y      : OUT std_logic); -- Enable next unit
END COMPONENT;

COMPONENT Mod_10_Counter
  PORT(Enable : IN std_logic;   -- Enable counter input
       Reset  : IN std_logic;   -- Reset on active low
       Clk    : IN std_logic;   -- Clock input
       DataOut: OUT std_logic_vector(3 DOWNTO 0);  -- 4 bits data OUT
       Y      : OUT std_logic); -- Enable next unit
END COMPONENT;

COMPONENT StopWatchCount
  PORT(StartStop  : IN std_logic;
       Reset      : IN std_logic;
       Clk        : IN std_logic;
       Tenths_OUT : OUT std_logic_vector(3 Downto 0);
       Seconds_OUT: OUT std_logic_vector(3 Downto 0);
       Tens_OUT   : OUT std_logic_vector(2 Downto 0));
END COMPONENT;

COMPONENT StopWatchBehave
  PORT(StartStop  : IN std_logic;
       Reset      : IN std_logic;
       Clk        : IN std_logic;
       Tenths_OUT : OUT integer;
       Seconds_OUT: OUT integer;
       Tens_OUT   : OUT integer);
END COMPONENT;

COMPONENT StopWatchReduce
  PORT(Clk_IN : IN std_logic;
       Enable : IN std_logic;
       Reset  : IN  std_logic;
       Clk_OUT: OUT std_logic);
END COMPONENT;

COMPONENT StopWatchStruc
  PORT(StartStop  : IN std_logic;
       Reset      : IN std_logic;
       Clk        : IN std_logic;
       Tenths_OUT : OUT std_logic_vector(3 Downto 0);
       Seconds_OUT: OUT std_logic_vector(3 Downto 0);
       Tens_OUT   : OUT std_logic_vector(2 Downto 0));
END COMPONENT;

END Stoppack;