--==========================================================
-- Design units : Display_Unit
--
-- File name    : StopWatchDisplay.vhd
--
-- Purpose      : Simulates a 7-Segment-Display
--
-- Limitations  : none
--
-- Library      : IEEE,GateLib
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    21.01.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;

ENTITY Display_Unit IS
PORT(Data  : IN  std_logic_vector(3 DOWNTO 0);
     Output: OUT std_logic_vector(6 DOWNTO 0));
END Display_Unit;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Display_Unit IS

SIGNAL not_Data : std_logic_vector(3 DOWNTO 0);
SIGNAL min : std_logic_vector(17 DOWNTO 0);
SIGNAL a,b,c,d,e,f,g: std_logic;

BEGIN

-- Generate inverted input signals

Loop1: FOR i IN 0 TO 3 GENERATE
  Invert_Input: INV
    PORT MAP(Data(i),not_Data(i));
  END GENERATE;

-- Generate Minterms for a

A_0: AND3
  PORT MAP(not_Data(1),Data(2),not_Data(3),min(0));
A_1: AND3
  PORT MAP(not_Data(1),not_Data(2),Data(3),min(1));
A_2: AND4
  PORT MAP(not_Data(0),Data(1),Data(2),not_Data(3),min(2));
A_3: AND4
  PORT MAP(not_Data(0),not_Data(1),not_Data(2),not_Data(3),min(3));

-- Generate Minterms for b

B_0: AND2
  PORT MAP(Data(1),not_Data(3),min(4));
B_1: AND3
  PORT MAP(not_Data(1),not_Data(2),Data(3),min(5));
-- next is min(3)
B_2: AND4
  PORT MAP(Data(0),not_Data(1),Data(2),not_Data(3),min(6));

-- Generate Minterms for c

C_0: AND2
  PORT MAP(not_Data(2),not_Data(3),min(7));
C_1: AND2
  PORT MAP(not_Data(1),not_Data(2),min(8));
C_2: AND4
  PORT MAP(Data(0),Data(1),Data(2),not_Data(3),min(9));
C_3: AND4
  PORT MAP(not_Data(0),not_Data(1),Data(2),not_Data(3),min(10));

-- Generate Minterms for d

-- next is min(1)
-- next is min(0)
D_0: AND3
  PORT MAP(Data(1),not_Data(2),not_Data(3),min(11));
-- next is min(2)

-- Generate Minterms for e

E_0: AND3
  PORT MAP(not_Data(0),Data(1),not_Data(3),min(12));
-- next is min(3)
E_1: AND4
  PORT MAP(not_Data(0),not_Data(1),not_Data(2),Data(3),min(13));

-- Generate Minterms for f
-- next is min(1)
F_0: AND3
  PORT MAP(not_Data(0),Data(1),not_Data(3),min(14));
-- next is min(6)
F_1: AND4
  PORT MAP(Data(0),Data(1),not_Data(2),not_Data(3),min(15));
-- next is min(3)

-- Generate Minterms for g
-- next is min(8)
G_0: AND2
  PORT MAP(Data(0),not_Data(3),min(16));
G_1: AND3
  PORT MAP(not_Data(0),Data(2),not_Data(3),min(17));

-- generate output

G_A: OR_4
  PORT MAP(min(0),min(1),min(2),min(3),a);

G_B: OR_4
  PORT MAP(min(4),min(5),min(3),min(6),b);

G_C: OR_4
  PORT MAP(min(7),min(8),min(9),min(10),c);

G_D: OR_4
  PORT MAP(min(1),min(0),min(11),min(2),d);

G_E: OR_3
  PORT MAP(min(12),min(3),min(13),e);

G_F: OR_5
  PORT MAP(min(1),min(14),min(6),min(15),min(3),f);

G_G: OR_3
  PORT MAP(min(8),min(16),min(17),g);

Output(0) <= a;
Output(1) <= b;
Output(2) <= c;
Output(3) <= d;
Output(4) <= e;
Output(5) <= f;
Output(6) <= g;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Display_Unit_Config OF Display_Unit IS
  FOR Structure
    FOR Loop1
      FOR Invert_Input: INV
        USE ENTITY work.inv(Behavior);
      END FOR;
    END FOR;
    FOR ALL : AND2
      USE ENTITY work.and2(Behavior);
    END FOR;
    FOR ALL : AND3
      USE ENTITY work.and3(Behavior);
    END FOR;
    FOR ALL : AND4
      USE ENTITY work.and4(Behavior);
    END FOR;
    FOR ALL : OR_3
      USE ENTITY work.or_3(Behavior);
    END FOR;
    FOR ALL : OR_4
      USE ENTITY work.OR_4(Behavior);
    END FOR;
    FOR G_F : OR_5
      USE ENTITY work.or_5(Behavior);
    END FOR;
  END FOR;
END Display_Unit_Config;