--==========================================================
-- Design units : Pulse_Generator (Entity,Architecture)
--
-- File name    : Pulse_Gen.vhd
--
-- Purpose      : Generates clock signal with 1 MHz
--
-- Limitations  : none
--
-- Library      : IEEE
--
-- Dependencies : ELEMpacck.vhd
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v 1.0  cjt    18.01.96       new
--=========================================================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;

ENTITY Pulse_Generator IS
  PORT(Clk : OUT std_logic := '0');
END Pulse_Generator;

--============================ARCHITECTURE==================

ARCHITECTURE Behavior OF Pulse_Generator I

  CONSTANT period: time := 1000 Ns;
  CONSTANT half_period : time := period/2;
  SIGNAL Pulse : std_logic := '0';

  BEGIN

    Generator: PROCESS

    BEGIN
 
      wait for half_period;

      Pulse <= not Pulse after 1 Ns;

    END PROCESS;

  Clk <= Pulse;

END Behavior;