--==========================================================
-- Design units : Mod_6_counter (Entity,Architecture,Configuration)
--
-- File name    : StopwatchMod6.vhd
--
-- Purpose      : Selfstarting MOD 6 counter
--
-- Limitations  : none
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    18.01.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.Stoppack.all;

ENTITY Mod_6_Counter IS
PORT(Enable : IN  std_logic;   -- Enable counter input
     Reset  : IN  std_logic;   -- Reset on active low
     Clk    : IN  std_logic;   -- Clock input
     DataOut: OUT std_logic_vector(2 DOWNTO 0);  -- 3 bits data OUT
     Y      : OUT std_logic);  -- Enable next unit
END Mod_6_Counter;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Mod_6_Counter IS

  SIGNAL count: std_logic_vector(2 DOWNTO 0);
  SIGNAL int_1,int_2,int_3,int_4,int_clk,y_OUT,y_OUT2: std_logic;
  SIGNAL one: std_logic := '1';

BEGIN

  X0: JK_FF_R         -- Toggle lsb
  PORT MAP(int_1,     -- jump
           one,     -- kill                war one
           int_clk,   -- clock input
           Reset,     -- asynchronous reset active low
           count(0),  -- state output
           open);

  X1: JK_FF_R         -- Toggle bit 1
  PORT MAP(int_2,     -- jump
           int_2,     -- kill
           int_clk,   -- clock input
           Reset,     -- asynchronous reset active low
           count(1),  -- state output
           open);

  X2: JK_FF_R         -- Toggle msb
  PORT MAP(int_3,     -- jump
           int_4,     -- kill
           int_clk,   -- clock input
           Reset,     -- asynchronous reset active low
           count(2),  -- state output
           open);

  Gate1: AND2         -- GENERATE internal clock SIGNAL
  PORT MAP(Enable,
           Clk,
           int_clk);

  Gate2: NAND2        -- GENERATE internal enable SIGNAL
  PORT MAP(count(0),  -- FOR FF 0
           count(2),
           int_1);

  Gate3: AND2         -- GENERATE internal enable SIGNAL
  PORT MAP(int_1,     -- FOR FF 1
           count(0),
           int_2);

  Gate4: AND2         -- GENERATE jump SIGNAL
  PORT MAP(int_2,     -- FOR FF 2
           count(1),
           int_3);

  Gate5: OR_2         -- GENERATE kill SIGNAL
  PORT MAP(int_3,     -- FOR FF 2
           y_OUT,
           int_4);

  Gate6: INV          -- GENERATE overflow SIGNAL
  PORT MAP(int_1,
           y_OUT);
 
  Gate7: AND2         -- Generate output pulse with clock width
  PORT MAP(int_clk,y_OUT,y_OUT2);


  Y <= y_OUT2;
  DataOut <= count;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Mod_6_Counter_Config OF Mod_6_Counter IS

  FOR Structure

    FOR ALL : JK_FF_R
      USE ENTITY work.jk_ff_r(Behavior);
    END FOR;

    FOR ALL : AND2
      USE ENTITY work.and2(Behavior);
    END FOR;

    FOR ALL : NAND2
      USE ENTITY work.nand2(Behavior);
    END FOR;

    FOR Gate5: OR_2
      USE ENTITY work.or_2(Behavior);
    END FOR;

    FOR Gate6: INV
      USE ENTITY work.inv(Behavior);
    END FOR;
  END FOR;
END Mod_6_Counter_Config;