LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.ELEMpack.all;

ENTITY nCMPN_s IS
  GENERIC(N : POSITIVE := 4);
  PORT(A : IN std_logic_vector(N-1 DOWNTO 0);
       B : IN std_logic_vector(N-1 DOWNTO 0);
       a_gr_b : OUT std_logic);
END nCMPN_s;

ARCHITECTURE Structure OF nCMPN_s IS

  SIGNAL a_sign,b_sign,not_a_sign,not_b_sign,a_ls_b,not_a_ls_b,int1,int2,int3 : std_logic;

  BEGIN

  a_sign <= A(N-1);
  b_sign <= B(N-1);



    Comparator: nCMPN
      GENERIC MAP(N-1)
      PORT MAP(A(N-2 DOWNTO 0),
               B(N-2 DOWNTO 0),
               open,
               a_ls_b);

    Gate1: INV
      PORT MAP(a_sign,
               not_a_sign);

    Gate2: INV
      PORT MAP(b_sign,
               not_b_sign);

    Gate3: INV
      PORT MAP(a_ls_b,
               not_a_ls_b);

    Gate4: AND3
      PORT MAP(not_a_sign,
               not_b_sign,
               not_a_ls_b,
               int1);

    Gate5: AND3
      PORT MAP(not_a_sign,
               b_sign,
               a_ls_b,
               int2);

    Gate6: AND2
      PORT MAP(b_sign,
               not_a_ls_b,
               int3);

    Gate7: OR_3
      PORT MAP(int1,
               int2,
               int3,
               a_gr_b);


END Structure;

CONFIGURATION nCMPN_s_Config OF nCMPN_s IS

  FOR Structure

    FOR Comparator: nCMPN
      USE ENTITY work.nCMPN(Structure);
    END FOR;

    FOR ALL : INV
      USE ENTITY work.inv(Behavior);
    END FOR;

    FOR ALL : AND3
      USE ENTITY work.AND3(Behavior);
    END FOR;

    FOR Gate7 : OR_3
      USE ENTITY work.or_3(Behavior);
    END FOR;

  END FOR;

END nCMPN_s_Config;