--==========================================================
-- Design units : MinMaxPack
--
-- File name    : MinMax_Pack.vhd
--
-- Purpose      : Package of required elements for the
--                MinMax-Circuit 
--
-- Limitations  : -
--
-- Library      : WORK
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    13.12.95       new
--=========================================================

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.ELEMpack.all;

PACKAGE MinMaxPack IS

  COMPONENT Three_to_four
    PORT(Clear      : IN std_logic;
         Enable     : IN std_logic;
         Reset      : IN std_logic;
         Condition1 : OUT std_logic;
         Condition2 : OUT std_logic;
         Condition3 : OUT std_logic;
         Condition4 : OUT std_logic);
  END COMPONENT;

  COMPONENT Last
    GENERIC(M: positive);
    PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
         Enable     : IN std_logic;
         Clk        : IN std_logic;
         LastOut    : OUT std_logic_vector(M-1 DOWNTO 0));
  END COMPONENT;
   
  COMPONENT Mean_value
    GENERIC(M: positive);
    PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
         Reset      : IN std_logic;
         Clk        : IN std_logic;
         MeanOut    : OUT std_logic_vector(M-1 DOWNTO 0));
  END COMPONENT;

  COMPONENT MinMaxStruc
    GENERIC(M: positive);
    PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
         Enable     : IN std_logic;
         Clk        : IN std_logic;
         Clear      : IN std_logic;
         Reset      : IN std_logic;
         DataOut    : OUT std_logic_vector(M-1 DOWNTO 0));
  END COMPONENT;

  COMPONENT MinMaxBehave
    GENERIC(M: positive);
    PORT(DataIn     : IN integer;
         Clear      : IN std_logic;
         Reset      : IN std_logic;
         Enable     : IN std_logic;
         Clk        : IN std_logic;
         DataOut    : OUT integer);
  END COMPONENT;

  COMPONENT MinMaxStim
    GENERIC (M : positive := 4);
    PORT(DataIn     : OUT std_logic_vector(M-1 DOWNTO 0);
         DataInBeh  : OUT integer;
         Enable     : OUT std_logic;
         Clk        : OUT std_logic;
         Clear      : OUT std_logic;
         Reset      : OUT std_logic);
  END COMPONENT;

  COMPONENT nCMPN_S
    GENERIC (N : positive := 4);
    PORT(A          : IN std_logic_vector(N-1 DOWNTO 0);
         B          : IN std_logic_vector(N-1 DOWNTO 0);
         a_gr_b     : OUT std_logic);
  END COMPONENT;

END MinMaxPack;