--==========================================================
-- Design units : Mean_value (Entity,Architecture,Configuration)
--
-- File name    : MinMax_MeanValue.vhd
--
-- Purpose      : Computation of Mean Value between stored
--                Maximum and Minimum
--
-- Limitations  :
--
-- Library      : WORK
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- v1.0    cjt    13.12.95       new
--=========================================================

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.MinMaxPack.all;

ENTITY Mean_value IS
  GENERIC(M: positive := 4);
  PORT(DataIn     : IN std_logic_vector(M-1 DOWNTO 0);
       Reset      : IN std_logic;
       Clk        : IN std_logic;
       MeanOut    : OUT std_logic_vector(M-1 DOWNTO 0));
END Mean_value;

--===========================ARCHITECTURE=================

ARCHITECTURE Structure OF Mean_value IS

SIGNAL out_great,out_less,not_Reset: std_logic;
SIGNAL out_mux1,out_mux2,out_mux3,out_mux4: std_logic_vector(M-1 DOWNTO 0);
SIGNAL out_max,out_min,out_mux3_r,out_mux1_r,out_add: std_logic_vector(M-1 DOWNTO 0);
SIGNAL zero: std_logic_vector(M-1 DOWNTO 0);
SIGNAL carry: std_logic;
SIGNAL zero_bit: std_logic := '0';

BEGIN

-- assign '0' to elements of zero

zero_loop:FOR i IN 0 TO M-1 GENERATE
  zero(i) <= '0';
END GENERATE;

Great_N : nCMPN_S        -- n-1 bit compare greater with msb sign
GENERIC MAP(M)
PORT MAP(DataIn,         -- Input A     
         out_max,        -- Input B
         out_great);     -- A > B

Less_N  : nCMPN_S        -- n-1 bit compare greater with msb sign
GENERIC MAP(M)
PORT MAP(DataIn,         -- Input A      
         out_min,        -- Input B
         out_less);      -- A > B

Mux_N_1 : nMUX           -- n bit 2:1 multiplexer
GENERIC MAP(M)
PORT MAP(out_max,        -- Input A0
         DataIn,         -- Input A1
         out_great,      -- select
         out_mux1);      -- = A0 IF select = 0

Mux_N_2 : nMUX           -- n bit 2:1 multiplexer
GENERIC MAP(M)
PORT MAP(zero,           -- Input A0
         out_mux1,       -- Input A1
         not_Reset,      -- select
         out_mux2);      -- = A0 IF select = 0

Mux_N_3 : nMUX           -- n bit 2:1 multiplexer
GENERIC MAP(M)
PORT MAP(DataIn,         -- Input A0
         out_min,        -- Input A1
         out_less,       -- select
         out_mux3);      -- = A0 IF select = 0

Mux_N_4 : nMUX           -- n bit 2:1 multiplexer
GENERIC MAP(M)
PORT MAP(zero,           -- Input A0
         out_mux3,       -- Input A1
         not_Reset,      -- select
         out_mux4);      -- = A0 IF select = 0

PastMax : nREG          -- n bit register
GENERIC MAP(M)
PORT MAP(Clk,            -- Clock Input
         Clk,            -- Select Input
         out_mux1_r,     -- Data In
         out_max);       -- Data Out

PastMin : nREG           -- n bit register
GENERIC MAP(M)
PORT MAP(Clk,            -- Clock Input
         Clk,            -- Select Input
         out_mux3_r,     -- Data In
         out_min);       -- Data Out

FullAdd : CRA            -- n bit carry ripple adder
GENERIC MAP(M)
PORT MAP(out_mux2,       -- Data In
         out_mux4,       -- Data In
         zero_bit,       -- Carry In
         out_add,        -- Sum Out
         open);         -- Carry Out

ShiftR  : nRSH           -- n bit shift right
GENERIC MAP(M)
PORT MAP(out_add,        -- Data In
         out_add(M-1),          -- Carry In
         MeanOut,        -- Data Out
         open);          -- Carry Out

Invert  : INV
PORT MAP(Reset,
         not_Reset);

-- Reset value '01...11' for minimum memory

AND_loop: FOR i IN 0 TO M-2 GENERATE
  OR_Gate_I: AND2
    PORT MAP(out_mux1(I),
             not_Reset,
             out_mux1_r(I));
END GENERATE;

Reset_MSB_Min: OR_2
  PORT MAP(out_mux1(M-1),
           Reset,
           out_mux1_r(M-1));

-- Reset value '10...00' for maximum memory

OR_loop: FOR i IN 0 TO M-2 GENERATE
  NOR_Gate_I: OR_2
    PORT MAP(out_mux3(I),
             Reset,
             out_mux3_r(I));
END GENERATE;

Reset_MSB_Max: AND2
  PORT MAP(out_mux3(M-1),
           not_Reset,
           out_mux3_r(M-1));

END Structure;

--===========================CONFIGURATION=================

CONFIGURATION Mean_value_config OF Mean_value IS

  FOR Structure

    FOR ALL : nCMPN_S          -- n-1 bit compare greater with msb sign
      USE ENTITY work.nCMPN_S(Structure);
    END FOR;

    FOR ALL : nMUX           -- n bit 2:1 multiplexer
      USE ENTITY work.nMUX(Structure);
    END FOR;

    FOR ALL : nREG          -- n bit register with reset
      USE ENTITY work.nREG(Structure);
    END FOR;

    FOR FullAdd : CRA            -- n bit carry ripple adder
      USE ENTITY work.cra(Structure);
    END FOR;

    FOR ShiftR  : nRSH           -- n bit shift right
      USE ENTITY work.nRSH(Structure);
    END FOR;

    FOR Invert  : INV
      USE ENTITY work.inv(Behavior);
    END FOR;

    FOR AND_loop
      FOR ALL:AND2
        USE ENTITY work.and2(Behavior);
      END FOR;
    END FOR;

    FOR Reset_MSB_Min: OR_2
      USE ENTITY work.or_2(Behavior);
    END FOR;

    FOR OR_loop
      FOR ALL:OR_2
        USE ENTITY work.or_2(Behavior);
      END FOR;
    END FOR;

    FOR Reset_MSB_Max: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;

  END FOR;

END Mean_value_config;