--========================================================== -- Design units : Entities,architectures and configurations -- for simple gates and gate structures -- -- File name : GateLib.vhd -- -- Purpose : often used gates and gate structures -- in benchmark descriptions, only the -- synthese subset of VHDL is used -- -- Limitations : File has to be compiled in the default -- library WORK -- -- Library : WORK -- -- Dependencies : IEEE -- -- Author : Hans-Peter Eich, REFT -- -- Simulator : Synopsys V3.1a on Sun SPARCstation 10 -- ----------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- V1.0 hpe 10.01.95 ESA-Standard -- V1.0 hpe 16.02.95 nCMPN,priority Structure -- V1.1 cjt 06.07.95 Change of OR2 to OR_2 --========================================================= -- -- Naming conventions: -- -- Cout : carry out Cin : carry in -- Q : state QZ : inverse state -- X : data in Y : data out -- A : data in B : data in -- C : data in D : data in -- S : select,store,set R : reset -- ls : less then eq : equal -- CLK : clock input -- --==================inverter=============================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY INV IS PORT (X: in std_logic; -- data in Y: out std_logic); -- data out END INV; ARCHITECTURE Behavior OF INV IS BEGIN main : PROCESS (X) BEGIN Y <= NOT X; END PROCESS; END Behavior; CONFIGURATION INV_DefaultConfig OF INV IS FOR Behavior END FOR; END INV_DefaultConfig; --==================buffer================================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY BUF IS PORT (X: IN std_logic; -- data in Y: OUT std_logic); -- data out END BUF; ARCHITECTURE Behavior OF BUF IS BEGIN main: PROCESS (X) BEGIN Y <= X; END PROCESS; END Behavior; CONFIGURATION BUF_DefaultConfig OF BUF IS FOR Behavior END FOR; END BUF_DefaultConfig; --==================n bit buffer=========================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nBUF IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(X: IN std_logic_vector(N-1 downto 0); -- n bit data in Y: OUT std_logic_vector(N-1 downto 0)); -- n bit data out END nBUF; ARCHITECTURE Structure OF nBUF IS BEGIN init: FOR i IN 0 TO N-1 GENERATE BufGate: BUF PORT MAP(X => X(i), Y => Y(i)); END GENERATE; END Structure; CONFIGURATION nBUF_DefaultConfig OF nBUF IS FOR Structure FOR init FOR BufGate : BUF USE ENTITY work.BUF(Behavior); END FOR; END FOR; END FOR; END nBUF_DefaultConfig; --==================NAND gate with 2 inputs================ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY NAND2 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END NAND2; ARCHITECTURE Behavior OF NAND2 IS BEGIN main: PROCESS (A,B) BEGIN Y <= A NAND B; END PROCESS; END Behavior; CONFIGURATION NAND2_DefaultConfig OF NAND2 IS FOR Behavior END FOR; END NAND2_DefaultConfig; --==================NAND gate with 3 inputs================ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY NAND3 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in Y: OUT std_logic); -- data out END NAND3; ARCHITECTURE Behavior OF NAND3 IS BEGIN main: PROCESS (A,B,C) BEGIN Y <= NOT (A AND B AND C); END PROCESS; END Behavior; CONFIGURATION NAND3_DefaultConfig OF NAND3 IS FOR Behavior END FOR; END NAND3_DefaultConfig; --==================AND gate with 2 inputs================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY AND2 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END AND2; ARCHITECTURE Behavior OF AND2 IS BEGIN main: PROCESS (A,B) BEGIN Y <= A AND B; END PROCESS; END Behavior; CONFIGURATION AND2_DefaultConfig OF AND2 IS FOR Behavior END FOR; END AND2_DefaultConfig; --==================AND gate with 3 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY AND3 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in Y: OUT std_logic); -- data out END AND3; ARCHITECTURE Behavior OF AND3 IS BEGIN main: PROCESS (A,B,C) BEGIN Y <= A AND B AND C; END PROCESS; END Behavior; CONFIGURATION AND3_DefaultConfig OF AND3 IS FOR Behavior END FOR; END AND3_DefaultConfig; --==================AND gate with 4 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY AND4 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in D: IN std_logic; -- data in Y: OUT std_logic); -- data out END AND4; ARCHITECTURE Behavior OF AND4 IS BEGIN main: PROCESS (A,B,C,D) BEGIN Y <= A AND B AND C AND D; END PROCESS; END Behavior; CONFIGURATION AND4_DefaultConfig OF AND4 IS FOR Behavior END FOR; END AND4_DefaultConfig; --==================AND gate with 5 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY AND5 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in D: IN std_logic; -- data in E: IN std_logic; -- data in Y: OUT std_logic); -- data out END AND5; ARCHITECTURE Behavior OF AND5 IS BEGIN main: PROCESS (A,B,C,D,E) BEGIN Y <= A AND B AND C AND D AND E; END PROCESS; END Behavior; CONFIGURATION AND5_DefaultConfig OF AND5 IS FOR Behavior END FOR; END AND5_DefaultConfig; --==================NOR gate with 2 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY NOR2 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END NOR2; ARCHITECTURE Behavior OF NOR2 IS BEGIN main: PROCESS (A,B) BEGIN Y <= A NOR B; END PROCESS; END Behavior; CONFIGURATION NOR2_DefaultConfig OF NOR2 IS FOR Behavior END FOR; END NOR2_DefaultConfig; --==================NOR gate with 3 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY NOR3 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in Y: OUT std_logic); -- data out END NOR3; ARCHITECTURE Behavior OF NOR3 IS BEGIN main: PROCESS (A,B,C) BEGIN Y <= NOT (A OR B OR C); END PROCESS; END Behavior; CONFIGURATION NOR3_DefaultConfig OF NOR3 IS FOR Behavior END FOR; END NOR3_DefaultConfig; --==================OR gate with 2 inputs================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY OR_2 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END OR_2; ARCHITECTURE Behavior OF OR_2 IS BEGIN main: PROCESS (A,B) BEGIN Y <= A OR B; END PROCESS; END Behavior; CONFIGURATION OR_2_DefaultConfig OF OR_2 IS FOR Behavior END FOR; END OR_2_DefaultConfig; --==================OR gate with 3 inputs================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY OR3 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in Y: OUT std_logic); -- data out END OR3; ARCHITECTURE Behavior OF OR3 IS BEGIN main: PROCESS (A,B,C) BEGIN Y <= A OR B OR C; END PROCESS; END Behavior; CONFIGURATION OR3_DefaultConfig OF OR3 IS FOR Behavior END FOR; END OR3_DefaultConfig; --==================OR gate with 4 inputs================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY OR4 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in D: IN std_logic; -- data in Y: OUT std_logic); -- data out END OR4; ARCHITECTURE Behavior OF OR4 IS BEGIN main: PROCESS (A,B,C,D) BEGIN Y <= A OR B OR C OR D; END PROCESS; END Behavior; CONFIGURATION OR4_DefaultConfig OF OR4 IS FOR Behavior END FOR; END OR4_DefaultConfig; --==================OR gate with 5 inputs================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY OR5 IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in C: IN std_logic; -- data in D: IN std_logic; -- data in E: IN std_logic; -- data in Y: OUT std_logic); -- data out END OR5; ARCHITECTURE Behavior OF OR5 IS BEGIN main: PROCESS (A,B,C,D,E) BEGIN Y <= A OR B OR C OR D OR E; END PROCESS; END Behavior; CONFIGURATION OR5_DefaultConfig OF OR5 IS FOR Behavior END FOR; END OR5_DefaultConfig; --==================NXOR gate with 2 inputs=============== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY NXOR2 IS PORT(A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END NXOR2; ARCHITECTURE Behavior OF NXOR2 IS BEGIN main:PROCESS (A,B) BEGIN Y <= NOT (A XOR B); END PROCESS; END Behavior; CONFIGURATION NXOR2_DefaultConfig OF NXOR2 IS FOR Behavior END FOR; END NXOR2_DefaultConfig; --==================XOR gate with 2 inputs================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY XOR2 IS PORT(A: IN std_logic; -- data in B: IN std_logic; -- data in Y: OUT std_logic); -- data out END XOR2; ARCHITECTURE Behavior OF XOR2 IS BEGIN main:PROCESS (A,B) BEGIN Y <= A XOR B; END PROCESS; END Behavior; CONFIGURATION XOR2_DefaultConfig OF XOR2 IS FOR Behavior END FOR; END XOR2_DefaultConfig; --==================2:1 multiplexer======================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY MUX IS PORT (A: IN std_logic; -- data in B: IN std_logic; -- data in S: IN std_logic; -- select input Y: OUT std_logic); -- data out END MUX; ARCHITECTURE Behavior OF MUX IS BEGIN main: PROCESS (A,B,S) BEGIN IF S='0' THEN Y <= A; ELSE Y <= B; END IF; END PROCESS; END Behavior; CONFIGURATION MUX_DefaultConfig OF MUX IS FOR Behavior END FOR; END MUX_DefaultConfig; --==================1:2 demultiplexer===================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY DMUX IS PORT( X: IN std_logic; -- data in S: IN std_logic; -- select output Y0: OUT std_logic; -- data out Y1: OUT std_logic); -- data out END DMUX; ARCHITECTURE Behavior OF DMUX IS BEGIN main:PROCESS (X,S) BEGIN IF (S='0') THEN Y0 <= X; Y1 <= '0'; ELSE Y0 <= '0'; Y1 <= X; END IF; END PROCESS; END Behavior; CONFIGURATION DMUX_DefaultConfig OF DMUX IS FOR Behavior END FOR; END DMUX_DefaultConfig; --==================delay latch=============================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY DL IS PORT ( D: IN std_logic; -- data in CLK: IN std_logic; -- clock in Q: OUT std_logic); -- state out END DL; ARCHITECTURE Behavior OF DL IS BEGIN main : PROCESS (D,CLK) BEGIN IF CLK='1' THEN Q <= D; END IF; END PROCESS; END Behavior; CONFIGURATION DL_DefaultConfig OF DL IS FOR Behavior END FOR; END DL_DefaultConfig; --==================delay flipflop====================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY DFF IS PORT ( D: IN std_logic; -- data in CLK: IN std_logic; -- clock in Q: OUT std_logic); -- state out END DFF; ARCHITECTURE Behavior OF DFF IS BEGIN main : PROCESS BEGIN WAIT UNTIL (CLK'EVENT AND CLK = '1'); Q <= D; END PROCESS; END Behavior; CONFIGURATION DFF_DefaultConfig OF DFF IS FOR Behavior END FOR; END DFF_DefaultConfig; --==================delay flipflop with set =============== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY DFFs IS PORT ( D: IN std_logic; -- data in S: IN std_logic; -- select data input CLK: IN std_logic; -- clock in Q: OUT std_logic; -- state out QZ: OUT std_logic); -- inverse state out END DFFs; ARCHITECTURE Behavior OF DFFs IS BEGIN main : PROCESS BEGIN WAIT UNTIL (CLK'EVENT AND CLK = '1'); IF (S = '1') THEN Q <= D; QZ <= NOT D; END IF; END PROCESS; END Behavior; CONFIGURATION DFFs_DefaultConfig OF DFFs IS FOR Behavior END FOR; END DFFs_DefaultConfig; --==================delay flipflop with select AND reset========= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY DFFsr IS PORT ( D: IN std_logic; -- data in S: IN std_logic; -- select data input R: IN std_logic; -- asynchronous reset active low CLK: IN std_logic; -- clock in Q: OUT std_logic); -- state out END DFFsr; ARCHITECTURE Behavior OF DFFsr IS BEGIN main : PROCESS (D,S,R,CLK) BEGIN IF (R = '0') THEN Q <= '0'; ELSE IF (CLK'EVENT AND CLK = '1') THEN IF (S = '1') THEN Q <= D; END IF; END IF; END IF; END PROCESS; END Behavior; CONFIGURATION DFFsr_DefaultConfig OF DFFsr IS FOR Behavior END FOR; END DFFsr_DefaultConfig; --==================rs flipflop with clear================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY RSFFR IS PORT (S: IN std_logic; -- set input R: IN std_logic; -- reset input C: IN std_logic; -- clear input QZ: OUT std_logic; -- inverse state out Q: OUT std_logic); -- state out END RSFFR; ARCHITECTURE Behavior OF RSFFR IS SIGNAL state : std_logic; BEGIN main : PROCESS (S,R,C) BEGIN IF R='1' THEN state <= '0'; ELSIF C='1' THEN state <= '0'; ELSIF S='1' THEN state <= '1'; END IF; END PROCESS; output_Q : PROCESS (state) BEGIN IF state='1' THEN Q <= '1'; ELSE Q <= '0'; END IF; END PROCESS; output_QZ : PROCESS (state) BEGIN IF state='0' THEN QZ <= '1'; ELSE QZ <= '0'; END IF; END PROCESS; END Behavior; CONFIGURATION RSFFR_DefaultConfig OF RSFFR IS FOR Behavior END FOR; END RSFFR_DefaultConfig; --==================rs flipflop====================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY RSFF IS PORT (S: IN std_logic; -- set input R: IN std_logic; -- reset input Q: OUT std_logic; -- state out QZ: OUT std_logic); -- inverse state out END RSFF; ARCHITECTURE Behavior OF RSFF IS SIGNAL state : std_logic; BEGIN main : PROCESS (S,R) BEGIN IF R='1' THEN state <= '0'; ELSIF S='1' THEN state <= '1'; END IF; END PROCESS; output_Q : PROCESS (state) BEGIN IF state='1' THEN Q <= '1'; ELSE Q <= '0'; END IF; END PROCESS; output_QZ : PROCESS (state) BEGIN IF state='0' THEN QZ <= '1'; ELSE QZ <= '0'; END IF; END PROCESS; END Behavior; CONFIGURATION RSFF_DefaultConfig OF RSFF IS FOR Behavior END FOR; END RSFF_DefaultConfig; --==================n bit 2:1 multiplexer================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nMUX IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(A0: IN std_logic_vector (N-1 DOWNTO 0); -- n bit data in A1: IN std_logic_vector (N-1 DOWNTO 0); -- n bit data in S: IN std_logic; -- select input Y: OUT std_logic_vector (N-1 DOWNTO 0)); -- n bit data out END nMUX; ARCHITECTURE Structure OF nMUX IS BEGIN init: FOR i IN 0 TO N-1 GENERATE MuxGate: MUX PORT MAP (A => A0(i), B => A1(i), S => S, Y => Y(i)); END GENERATE; END Structure; CONFIGURATION nMUX_DefaultConfig OF nMUX IS FOR Structure FOR init FOR MuxGate : MUX USE ENTITY work.MUX(Behavior); END FOR; END FOR; END FOR; END nMUX_DefaultConfig; --==================n bit 1:2 demultiplexer=============== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nDMUX IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(X: IN std_logic_vector (N-1 DOWNTO 0); -- n bit data in S: IN std_logic; -- select output Y0: OUT std_logic_vector (N-1 DOWNTO 0); -- n bit data out Y1: OUT std_logic_vector (N-1 DOWNTO 0)); -- n bit data out END nDMUX; ARCHITECTURE Structure OF nDMUX IS BEGIN init: FOR i IN 0 TO N-1 GENERATE DMuxGate : DMUX PORT MAP (X => X(i), S => S, Y0 => Y0(i), Y1 => Y1(i)); END GENERATE; END Structure; CONFIGURATION nDMUX_DefaultConfig OF nDMUX IS FOR Structure FOR init FOR DMuxGate : DMUX USE ENTITY work.DMUX(Behavior); END FOR; END FOR; END FOR; END nDMUX_DefaultConfig; --==================n bit register==================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nREG IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(CLK: IN std_logic; -- clock in S: IN std_logic; -- select data input X: IN std_logic_vector (N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic_vector (N-1 DOWNTO 0)); -- n bit data out END nREG; ARCHITECTURE Structure OF nREG IS BEGIN init: FOR i IN 0 TO N-1 GENERATE DFFsGate: DFFs PORT MAP ( D => X(i), S => S, CLK => CLK, Q => Y(i), QZ => OPEN); END GENERATE; END Structure; CONFIGURATION nREG_DefaultConfig OF nREG IS FOR Structure FOR init FOR DFFsGate : DFFs USE ENTITY work.DFFs(Behavior); END FOR; END FOR; END FOR; END nREG_DefaultConfig; --==================n bit register with reset============== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nREGr IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(CLK: IN std_logic; -- clock in S: IN std_logic; -- select data input R: IN std_logic; -- asynchronous reset X: IN std_logic_vector (N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic_vector (N-1 DOWNTO 0)); -- n bit data out END nREGr; ARCHITECTURE Structure OF nREGr IS SIGNAL Data: std_logic_vector(N-1 DOWNTO 0); BEGIN init : FOR i IN 0 TO N-1 GENERATE DFFsrGate : DFFsr PORT MAP (D => X(i), S => S, R => R, CLK => CLK, Q => Y(i)); END GENERATE; END Structure; CONFIGURATION nREGr_DefaultConfig OF nREGr IS FOR Structure FOR init FOR DFFsrGate : DFFsr USE ENTITY work.DFFsr(Behavior); END FOR; END FOR; END FOR; END nREGr_DefaultConfig; --==================half adder============================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY HA IS PORT (A : IN std_logic; -- data in B : IN std_logic; -- data in Sum : OUT std_logic; -- sum out Cout: OUT std_logic); -- carry out END HA; ARCHITECTURE Structure OF HA IS BEGIN XorGate: XOR2 PORT MAP(A => A, B => B, Y => Sum); AndGate: AND2 PORT MAP(A => A, B => B, Y => Cout); END Structure; CONFIGURATION HA_DefaultConfig OF HA IS FOR Structure FOR XorGate : XOR2 USE ENTITY work.XOR2(Behavior); END FOR; FOR AndGate : AND2 USE ENTITY work.AND2(Behavior); END FOR; END FOR; END HA_DefaultConfig; --==================full adder============================ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY FA IS PORT(A : IN std_logic; -- data in B : IN std_logic; -- data in Cin : IN std_logic; -- carry in Sum : OUT std_logic; -- sum out Cout : OUT std_logic); -- carry out END FA; ARCHITECTURE Structure OF FA IS SIGNAL tsum,tcarry0,tcarry1: std_logic; BEGIN HaGate_1: HA PORT MAP(A => A, B => B, Sum => tsum, Cout => tcarry0); HaGate_2: HA PORT MAP(A => Cin, B => tsum, Sum => Sum, Cout => tcarry1); OrGate_1: OR_2 PORT MAP(A => tcarry0, B => tcarry1, Y => Cout); END Structure; CONFIGURATION FA_DefaultConfig OF FA IS FOR Structure FOR HaGate_1 : HA USE ENTITY work.HA(Structure); END FOR; FOR HaGate_2 : HA USE ENTITY work.HA(Structure); END FOR; FOR OrGate_1 : OR_2 USE ENTITY work.OR_2(Behavior); END FOR; END FOR; END FA_DefaultConfig; --==================n bit increment================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nINC IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out Cout: OUT std_logic); -- cary out END nINC; ARCHITECTURE Structure OF nINC IS SIGNAL temp : std_logic_vector(N DOWNTO 0); BEGIN temp(0) <= '1'; init: FOR i IN 0 TO N-1 GENERATE half_adder : HA PORT MAP( A => temp(i), B => X(i), Sum => Y(i), Cout => temp(i+1)); END GENERATE; Cout <= temp(N); END Structure; CONFIGURATION nINC_DefaultConfig OF nINC IS FOR Structure FOR init FOR half_adder : HA USE ENTITY work.HA(Structure); END FOR; END FOR; END FOR; END nINC_DefaultConfig; --==================n bit carry ripple adder============== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY CRA IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT (A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Cin: IN std_logic; -- carry in Sum: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out Cout: OUT std_logic); -- carry out END CRA; ARCHITECTURE Structure OF CRA IS SIGNAL temp: std_logic_vector(N DOWNTO 0); BEGIN temp(0) <= Cin; init: FOR i IN 0 TO N-1 GENERATE full_adder : FA PORT MAP( A => A(i), B => B(i), Cin => temp(i), Sum => Sum(i), Cout => temp(i+1)); END GENERATE; Cout <= temp(N); END Structure; CONFIGURATION CRA_DefaultConfig OF CRA IS FOR Structure FOR init FOR full_adder : FA USE ENTITY work.FA(Structure); END FOR; END FOR; END FOR; END CRA_DefaultConfig; --==================n bit adder/subtractor================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY AddSub IS GENERIC (N: POSITIVE := 4); -- default n = 4 PORT ( A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Mode: IN std_logic; -- mode 0 add, 1 sub Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out Cout: OUT std_logic); -- carry out END AddSub; ARCHITECTURE Structure OF AddSub IS SIGNAL invert: std_logic_vector (N-1 DOWNTO 0); SIGNAL carry: std_logic_vector (N DOWNTO 0); BEGIN carry(0) <= Mode; init: FOR i IN 0 TO N-1 GENERATE XorGate : XOR2 PORT MAP(A => B(i), B => Mode, Y => invert(i)); full_adder : FA PORT MAP(A => invert(i), B => A(i), Cin => carry(i), Sum => Y(i), Cout => carry(i+1)); END GENERATE; Cout <= carry(N); END Structure; CONFIGURATION AddSub_DefaultConfig OF AddSub IS FOR Structure FOR init FOR XorGate : XOR2 USE ENTITY work.XOR2(Behavior); END FOR; FOR full_adder : FA USE ENTITY work.FA(Structure); END FOR; END FOR; END FOR; END AddSub_DefaultConfig; --==================n bit shift register================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nSREG IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in S: IN std_logic; -- select input or shift CLK: IN std_logic; -- clock in Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out END nSREG; ARCHITECTURE Structure OF nSREG IS SIGNAL shift: std_logic_vector (2*N DOWNTO 0); BEGIN init: FOR i IN 0 TO N-1 GENERATE BufGate : BUF PORT MAP(X => shift(2*i), Y => Y(i)); DffGate : DFF PORT MAP( D => shift(2*i), CLK => CLK, Q => shift(2*i+1)); MuxGate : MUX PORT MAP (A => shift(2*i+1), B => X(i), S => S, Y => shift(2*i+2)); END GENERATE; paste : BUF PORT MAP(X => shift(2*N), Y => shift(0)); END Structure; CONFIGURATION nSREG_DefaultConfig OF nSREG IS FOR Structure FOR init FOR BufGate : BUF USE ENTITY work.BUF(Behavior); END FOR; FOR DffGate : DFF USE ENTITY work.DFF(Behavior); END FOR; FOR MuxGate : MUX USE ENTITY work.MUX(Behavior); END FOR; END FOR; FOR paste : BUF USE ENTITY work.BUF(Behavior); END FOR; END FOR; END nSREG_DefaultConfig; --==================n bit compare equal zero================ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nCMP0 IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic); -- equal zero END nCMP0; ARCHITECTURE Structure OF nCMP0 IS SIGNAL wired_or: std_logic_vector(N-1 DOWNTO 0); BEGIN wired_or(0) <= X(0); init : FOR i IN 0 TO N-2 GENERATE OrGate : OR_2 PORT MAP(A => X(i+1), B => wired_or(i), Y => wired_or(i+1)); END GENERATE; InvGate: INV PORT MAP(X => wired_or(N-1), Y => Y); END Structure; CONFIGURATION nCMP0_DefaultConfig OF nCMP0 IS FOR Structure FOR init FOR OrGate : OR_2 USE ENTITY work.OR_2(Behavior); END FOR; END FOR; FOR InvGate : INV USE ENTITY work.INV(Behavior); END FOR; END FOR; END nCMP0_DefaultConfig; --==================n bit compare equal less=================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nCMPN IS GENERIC (N: POSITIVE := 4); -- default n = 4 PORT (A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in eq: OUT std_logic; -- A equals B ls: OUT std_logic); -- A is less then B END nCMPN; ARCHITECTURE Structure OF nCMPN IS SIGNAL VDD,Carry : std_logic; SIGNAL Sum : std_logic_vector(N-1 DOWNTO 0); BEGIN VDD <= '1'; Subtract : AddSub GENERIC MAP(N) PORT MAP(A => A, B => B, Mode => VDD, Y => Sum, Cout => Carry); Invert : INV PORT MAP (X => Carry, Y => ls); Compare : nCMP0 GENERIC MAP(N) PORT MAP (X => Sum, Y => eq); END Structure; CONFIGURATION nCMPN_Config OF nCMPN IS FOR Structure FOR Subtract : AddSub USE ENTITY work.AddSub(Structure); END FOR; FOR Invert : INV USE ENTITY work.INV(Behavior); END FOR; FOR Compare : nCMP0 USE ENTITY work.nCMP0(Structure); END FOR; END FOR; END nCMPN_Config; --==================n bit shift left========================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nLSH IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Cin: IN std_logic; -- carry in Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out Cout: OUT std_logic); -- carry out END nLSH; ARCHITECTURE Structure OF nLSH IS BEGIN Y(0) <= Cin; init : FOR i IN 1 TO N-1 GENERATE Y(i) <= X(i-1); END GENERATE; Cout <= X(N-1); END Structure; CONFIGURATION nLSH_DefaultConfig OF nLSH IS FOR Structure END FOR; END nLSH_DefaultConfig; --==================n bit shift right======================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY nRSH IS GENERIC(N: POSITIVE := 4); -- default n = 4 PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Cin: IN std_logic; -- carry in Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out Cout: OUT std_logic); -- carry out END nRSH; ARCHITECTURE Structure OF nRSH IS BEGIN Y(N-1) <= Cin; init : FOR i IN 1 TO N-1 GENERATE Y(i-1) <= X(i); END GENERATE; Cout <= X(0); END Structure; CONFIGURATION nRSH_DefaultConfig OF nRSH IS FOR Structure END FOR; END nRSH_DefaultConfig; --==================expand bit vector======================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY expand IS GENERIC(N : POSITIVE := 4; -- default n = 4 M : POSITIVE := 8); -- default m = 8 PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic_vector(M-1 DOWNTO 0)); -- m bit data out END expand; ARCHITECTURE Structure OF expand IS BEGIN first : FOR i IN 0 TO N-1 GENERATE Y(i) <= X(i); END GENERATE; last : FOR j IN N TO M-1 GENERATE Y(j) <= '0'; END GENERATE; END Structure; CONFIGURATION expand_DefaultConfig OF expand IS FOR Structure END FOR; END expand_DefaultConfig; --==================priority check============================== LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.ELEMpack.ALL; ENTITY priority IS GENERIC (N: POSITIVE := 4); -- default n = 4 PORT (X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out END priority; ARCHITECTURE Structure OF priority IS SIGNAL Not_X : std_logic_vector(N-1 DOWNTO 0); SIGNAL wired_and : std_logic_vector (N*(N-1) DOWNTO 0); BEGIN Y(0) <= X(0); general_case : IF N>1 GENERATE row : FOR i IN 1 TO N-1 GENERATE column : FOR j IN 1 TO N-1 GENERATE invert : IF j=1 GENERATE InvGate : INV PORT MAP (X => X(i-1), Y => Not_X(i-1)); wired_and(N*(i-1)) <= X(i); -- connect inputs END GENERATE; output_and : IF i=j GENERATE AndGate_1 : AND2 PORT MAP (A => Not_X(j-1), B => wired_and(N*(i-1)+(j-1)), Y => Y(i)); END GENERATE; internal_and : IF j Not_X(j-1), B => wired_and(N*(i-1)+(j-1)), Y => wired_and(N*(i-1)+j)); END GENERATE; END GENERATE; END GENERATE; END GENERATE; END Structure; CONFIGURATION priority_Config OF priority IS FOR Structure FOR general_case FOR row FOR column FOR invert FOR InvGate : INV USE ENTITY work.INV(Behavior); END FOR; END FOR; FOR output_and FOR AndGate_1 : AND2 USE ENTITY work.AND2(Behavior); END FOR; END FOR; FOR internal_and FOR AndGate_2 : AND2 USE ENTITY work.AND2(Behavior); END FOR; END FOR; END FOR; END FOR; END FOR; END FOR; END priority_Config;