--==========================================================
-- Design units : FiFoStructure
--
-- File name    : FIFOstruc.vhd
--
-- Purpose      : Complete FIFO Storage-Circuit
--
-- Limitations  : 
--
-- Library      : work
--
-- Dependencies : FIFOstage, FIFOpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95
-- V2.0    cjt    16.11.95       std_logic, configuration, ESA-standard
--===========================================================

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.FIFOpack.all;

ENTITY FIFOstruc IS
  GENERIC (M: Positive := 4; -- word length
    	   N: Positive := 4);-- Number of stages
  PORT (DataIn      : IN std_logic_vector(M-1 DOWNTO 0);
        ShiftIn     : IN std_logic;
        ShiftOut    : IN std_logic;
        MasterReset : IN std_logic;
        DataOut     : OUT std_logic_vector(M-1 DOWNTO 0);
        InputReady  : OUT std_logic_vector(0 to 0);
        OutputReady : OUT std_logic_vector(0 to 0));    
END FIFOstruc;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF FIFOstruc IS

  TYPE Logic_data IS ARRAY (Natural RANGE <>) OF std_logic_vector(M-1 DOWNTO 0); 
  SIGNAL Data: Logic_data(N-1 DOWNTO 0);
  SIGNAL MoveReady,Reset: std_logic_vector(N-1 DOWNTO 0);

BEGIN

U0: FOR I IN 0 to N-1 GENERATE

  one: IF I=0 AND N=1 GENERATE
    C0: FIFOstage
      GENERIC MAP(M)
      PORT MAP(DataIn,ShiftIn,ShiftOut,MasterReset,DataOut,
               InputReady(0),open,OutputReady(0));
  END GENERATE;

  two: IF I=0 AND N=2 GENERATE
    C1: FIFOstage
      GENERIC MAP(M)
      PORT MAP(DataIn,ShiftIn,Reset(0),MasterReset,Data(0),
               InputReady(0),open,MoveReady(0));
    C2: FIFOstage
      GENERIC MAP(M)
      PORT MAP(Data(0),MoveReady(0),ShiftOut,MasterReset,DataOut,
               open,Reset(0),OutputReady(0));
    END GENERATE;

    first: IF I=0 AND N>2 GENERATE 
      F0: FIFOstage
	GENERIC MAP(M)
	PORT MAP(DataIn,ShiftIn,Reset(0),MasterReset,Data(0),
                 InputReady(0),open,MoveReady(0));
    END GENERATE;

    middle: IF I>0 AND I<N-1 AND N>2 GENERATE
      F1: FIFOstage
	GENERIC MAP(M)
	PORT MAP(Data(I-1),MoveReady(I-1),Reset(I),MasterReset,Data(I),
                 open,Reset(I-1),MoveReady(I));
      END GENERATE;

    last: IF I=N-1 AND N>2 GENERATE
      F2: FIFOstage
	GENERIC MAP(M)
	PORT MAP(Data(I-1),MoveReady(I-1),ShiftOut,MasterReset,DataOut,
                 open,Reset(I-1),OutputReady(0));
      END GENERATE;

END GENERATE;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION FIFOstruc_config OF FIFOstruc IS

FOR Structure

    FOR U0

      FOR one
	FOR C0: FIFOstage
	  USE ENTITY work.FIFOstage(Structure);
	END FOR;
      END FOR;

      FOR two
	FOR all : FIFOstage
	  USE ENTITY work.FIFOstage(Structure);
	END FOR;
      END FOR; -- two

      FOR first
	FOR F0: FIFOstage
	  USE ENTITY work.FIFOstage(Structure);
	END FOR;
      END FOR;

      FOR middle
	FOR F1: FIFOstage
	  USE ENTITY work.FIFOstage(Structure);
	END FOR;
      END FOR;

      FOR last
	FOR F2: FIFOstage
	  USE ENTITY work.FIFOstage(Structure);
	END FOR;
      END FOR;

    END FOR;  --U0

  END FOR; -- Structure

END FIFOstruc_config;