--========================================================== -- Design units : FiFoStage -- -- File name : FIFOstage.vhd -- -- Purpose : Implementation of one stage for FIFO -- -- Limitations : -- -- Library : work -- -- Dependencies : -- -- Author : Hans-Peter Eich, REFT -- -- Simulator : Synopsys V3.1a on SUN SPARCstation 10 -- ------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- V1.0 hpe 02.04.95 -- V2.0 cjt 01.11.95 std_logic, configuration, ESA-standard --=========================================================== LIBRARY IEEE; USE ieee.std_logic_1164.all; USE work.FIFOpack.all; ENTITY FIFOstim IS GENERIC (M: POSITIVE := 4); PORT (DataInInt : OUT INTEGER; DataIn : OUT std_logic_vector(M-1 DOWNTO 0); ShiftIn : OUT std_logic; ShiftOut : OUT std_logic; MasterReset : OUT std_logic); END FIFOstim; ARCHITECTURE Behavior OF FIFOstim IS BEGIN -- Test 1: working of InputReady MasterReset <= '0' AFTER 10 Ns, '1' AFTER 20 Ns, '0' AFTER 30 Ns; DataInInt <= 3 AFTER 50 Ns, 0 AFTER 100 Ns, 14 AFTER 150 Ns, 0 AFTER 200 Ns, 10 AFTER 250 Ns, 0 AFTER 300 Ns, 8 AFTER 350 Ns, 0 AFTER 400 Ns, 5 AFTER 450 Ns, 0 AFTER 500 Ns; DataIn <= "0011" AFTER 50 Ns, "0000" AFTER 100 Ns, "1110" AFTER 150 Ns, "0000" AFTER 200 Ns, "1010" AFTER 250 Ns, "0000" AFTER 300 Ns, "1000" AFTER 350 Ns, "0000" AFTER 400 Ns, "0101" AFTER 450 Ns, "0000" AFTER 500 Ns; ShiftIn <= '0' AFTER 2 Ns, '1' AFTER 55 Ns, '0' AFTER 60 Ns, '1' AFTER 165 Ns, '0' AFTER 170 Ns, '1' AFTER 255 Ns, '0' AFTER 260 Ns, '1' AFTER 355 Ns, '0' AFTER 360 Ns, '1' AFTER 455 Ns, '0' AFTER 460 Ns, '1' AFTER 550 Ns, '0' AFTER 560 Ns, '1' AFTER 600 Ns, '0' AFTER 610 Ns, '1' AFTER 650 Ns, '0' AFTER 660 Ns; -- Test 2: working of OutputReady ShiftOut <= '0' AFTER 10 Ns, '1' AFTER 270 Ns, '0' AFTER 280 Ns, '1' AFTER 370 Ns, '0' AFTER 380 Ns, '1' AFTER 670 Ns, '0' AFTER 680 Ns, '1' AFTER 720 Ns, '0' AFTER 730 Ns, '1' AFTER 770 Ns, '0' AFTER 780 Ns, '1' AFTER 820 Ns, '0' AFTER 830 Ns, '0' AFTER 870 Ns; END Behavior;