--==========================================================
-- Design units : FiFoBehavior
--
-- File name    : FIFObehave.vhd
--
-- Purpose      : Specification of a FIFO memory device by 
--
--                behavioral description
--
-- Limitations  : none
--
-- Library      : work
--
-- Dependencies : none
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95       new
-- V2.0    cjt    16.11.95       new description, very close
--                               to the real structure
--===========================================================

LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY FIFObehave IS
  GENERIC(N         : Positive);       -- Number of memory cells
  PORT(DataIn       : IN Integer;
       ShiftIn      : IN std_logic;
       ShiftOut     : IN std_logic;
       MasterReset  : IN std_logic;
       DataOut      : OUT Integer;
       MemoryFlag   : INOUT std_logic_vector(N-1 DOWNTO 0);
       InputReady   : INOUT std_logic;
       OutputReady  : INOUT std_logic);
END FIFObehave;

--============================ARCHITECTURE==================

ARCHITECTURE Behavior OF FIFObehave IS

TYPE INT_vector IS ARRAY (Natural range <>) OF NATURAL;
SIGNAL Memory: INT_vector(N-1 DOWNTO 0);

BEGIN

  In_Out : PROCESS(ShiftIn, ShiftOut,MasterReset,MemoryFlag,
                   InputReady,OutputReady)

  BEGIN

    -- Read data from outside

    IF InputReady = '1' AND ShiftIn = '1' THEN
      Memory(0) <= DataIn AFTER 5 Ns;
      MemoryFlag(0) <= '1' AFTER 5 Ns;
    END IF;

    -- Data have been read from outside

    IF OutputReady = '1' AND ShiftOut = '1' THEN
      MemoryFlag(N-1) <= '0' AFTER 5 Ns;
    END IF;

    -- Bubble through of data

    IF MemoryFlag'event THEN

      FOR I IN N-1 DOWNTO 1 LOOP

        IF MemoryFlag(I) = '0' THEN
          Memory(I) <= Memory(I-1) AFTER 5 Ns;
          MemoryFlag(I) <= MemoryFlag(I-1) AFTER 5 Ns;
          MemoryFlag(I-1) <= '0' AFTER 5 Ns;
        END IF; 

      END LOOP;
 
    END IF;

    -- Reset: set MemoryFlags to 0

    IF MasterReset = '1' THEN
      FOR I IN N-1 DOWNTO 0 LOOP
        MemoryFlag(I) <= '0' AFTER 5 Ns;
      END LOOP;
    END IF;

  END PROCESS;

  Ready: PROCESS(MasterReset,MemoryFlag)

    BEGIN

      -- Generate OutputReady signal

      IF MemoryFlag(N-1) = '0' THEN
        OutputReady <= '0' AFTER 5 Ns;
      ELSE
        OutputReady <= '1' AFTER 5 Ns;
      END IF;

      -- Generate InputReady signal

      IF MemoryFlag(0) = '1' THEN
        InputReady <= '0' AFTER 5 Ns;
      ELSE
        InputReady <= '1' AFTER 5 Ns;
      END IF;

      -- Reset of InputReady and OutputReady

      IF MasterReset = '1' THEN
        InputReady <= '1' AFTER 5 Ns;
        OutputReady <= '0' AFTER 5 Ns;
      END IF;

  END PROCESS;

  Output: PROCESS(OutputReady)
 
    BEGIN

      -- Release data when ready

      IF OutputReady = '1' THEN
        DataOut <= Memory(N-1) AFTER 5 Ns;
      END IF;
  
  END PROCESS;


END Behavior;