--========================================================== -- Design units : DIVstim (stimuli) -- -- File name : DIVstim.vhd -- -- Purpose : Stimuli generator for divider array -- -- Limitations : None -- -- Library : WORK -- -- Dependencies : IEEE, DIVpack -- -- Author : Claus-Juergen Thomas, REFT -- -- Simulator : Synopsys V3.1a on SUN SPARCstation 10 -- ----------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- V1.0 cjt 09.09.95 new --========================================================= LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.DIVpack.ALL; ENTITY DIVstim IS GENERIC ( M: POSITIVE := 3; -- bit lenght of divisor K: POSITIVE := 6); -- bit lenght of dividend PORT ( N_test : OUT Integer RANGE (2**K)-1 DOWNTO 0; -- integer divisor D_test : OUT Integer RANGE (2**M)-1 DOWNTO 0; -- integer dividend Nvec_test: OUT std_logic_vector((K-1) DOWNTO 0); -- binary divisor Dvec_test: OUT std_logic_vector((M-1) DOWNTO 0)); -- binary dividend END DIVstim; --============================ARCHITECTURE================== ARCHITECTURE Behavior OF DIVstim IS BEGIN N_test <= 0 AFTER 0 Ns, 15 AFTER 10 Ns, 10 AFTER 50 Ns, 5 AFTER 100 Ns, 1 AFTER 150 Ns, 15 AFTER 200 Ns; D_test <= 0 AFTER 0 Ns, 7 AFTER 10 Ns, 5 AFTER 50 Ns, 2 AFTER 100 Ns, 3 AFTER 150 Ns, 1 AFTER 200 Ns; Nvec_test <= ("000000") AFTER 0 Ns, -- 0 ("001111") AFTER 10 Ns, -- 15 ("001010") AFTER 50 Ns, -- 10 ("000101") AFTER 100 Ns, -- 5 ("000001") AFTER 150 Ns, -- 1 ("001111") AFTER 200 Ns; -- 15 Dvec_test <= ("000") AFTER 0 Ns, -- 0 ("111") AFTER 10 Ns, -- 7 ("101") AFTER 50 Ns, -- 5 ("010") AFTER 100 Ns, -- 2 ("011") AFTER 150 Ns, -- 3 ("001") AFTER 200 Ns; -- 1 END Behavior; --============================CONFIGURATION================= CONFIGURATION DIVstim_Config OF DIVstim IS FOR Behavior END FOR; END DIVstim_Config;