--==========================================================
-- Design units : DIVoutput 
--                (entity, architecture and configuration)
--
-- File name    : DIVoutput.vhd
--
-- Purpose      : output unit for result of division
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : IEEE,ELEMpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    20.01.95       ESA standard
-- V2.0    cjt    23.09.95       Change of OR-Gates
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.ELEMpack.ALL;

ENTITY DIVOUTput IS
  PORT (A: IN std_logic;   -- data in
        B: IN std_logic;   -- data in
        Y: OUT std_logic;  -- data out
       nY: OUT std_logic); -- data out
END DIVOUTput;

-- if the most signifikant bit of the dividend equals '1' or
-- the result of the subtraction is not negative then set
-- quotient bit to '1' else set quotient bit to zero and
-- restore the dividend through nY := '1'

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF DIVOUTput IS

  SIGNAL temp,yout: std_logic;

BEGIN

  InvGate_1 : INV
    PORT MAP(X => B,
             Y => temp);

  OrGate : OR_2
    PORT MAP(A => A,
             B => temp,
             Y => yout);

  InvGate_2 : INV
    PORT MAP(X => yout,
             Y => nY);

  Y <= yout;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION DIVoutput_Config OF DIVoutput IS
  FOR Structure
    FOR ALL : INV
      USE ENTITY work.INV(Behavior);
    END FOR;
    FOR ALL : OR_2
      USE ENTITY work.OR_2(Behavior);
    END FOR;
  END FOR;
END DIVoutput_Config;