--==========================================================
-- Design units : DIVcell
--                (entity, architecture and configuration)
--
-- File name    : DIVcell.vhd
--
-- Purpose      : cell description for divider array
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : IEEE, ELEMpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    19.01.95       ESA standard
-- V1.0    hpe    02.04.95       abreviations
-- V2.0    cjt    23.09.95       Change of OR-Gates
--=========================================================
--
-- A : partial remainder in
-- B : divisor bit
-- C : borrow in
-- D : subtract control
-- P : borrow out
-- S : difference

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.ELEMpack.ALL;

ENTITY DIVcell IS
  PORT (DivIn: IN std_logic;      -- divisor bit in 
        Rem1: IN std_logic;       -- rmainder of dividend in
        BorrowIn: IN std_logic;   -- carry in
        SubIn: IN std_logic;      -- restore subtraction in
        BorrowOut: OUT std_logic; -- carry out
        SubOut: OUT std_logic;    -- restore subtrction out
        DivOut: OUT std_logic;    -- divisor bit out
        Dif: OUT std_logic);      -- diference out
END DIVcell;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF DIVcell IS
  SIGNAL A,B,C,D,P,S,P_1,P_2,P_3,S_1,S_2,S_3,S_4,S_5 : std_logic;
  SIGNAL Not_A,Not_B,Not_C,Not_D : std_logic;
BEGIN

  -- input signals

  A <= Rem1;
  B <= DivIn;
  C <= BorrowIn;
  D <= SubIn;

  -- output signals

  BorrowOut <= P;
  SubOut <= D;
  DivOut <= B;
  Dif <= S;
 
  -- gates

  Invert_A : INV
    PORT MAP(X => A,
             Y => Not_A);

  Invert_B : INV
    PORT MAP(X => B,
             Y => Not_B);

  Invert_C : INV
    PORT MAP(X => C,
             Y => Not_C);

  Invert_D : INV 
    PORT MAP(X => D,
             Y => Not_D);
  
  And_P_1 : AND2
    PORT MAP(A => Not_A,
             B => C,
             Y => P_1);

  And_P_2 : AND2
    PORT MAP(A => Not_A,
             B => B,
             Y => P_2);

  And_P_3 : AND2
    PORT MAP(A => B,
             B => C,
             Y => P_3);

  Or_P : OR_3
    PORT MAP(A => P_1,
             B => P_2,
             C => P_3,
             Y => P);

  And_S_1 : AND4
    PORT MAP(A => Not_A,
             B => B,
             C => Not_C,
             D => Not_D,
             Y => S_1);

  And_S_2 : AND4
    PORT MAP(A => Not_A,
             B => Not_B, 
             C => C,
             D => Not_D,
             Y => S_2);

  And_S_3 : AND3
    PORT MAP(A => A,
             B => B,
             C => C,
             Y => S_3);

  And_S_4 : AND3
    PORT MAP(A => A,
             B => Not_B,
             C => Not_C,
             Y => S_4);

  And_S_5 : AND2
    PORT MAP(A => A,
             B => D,
             Y => S_5);

  Or_S : OR5
    PORT MAP(A => S_1,
             B => S_2,
             C => S_3,
             D => S_4,
             E => S_5,
             Y => S);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION DIVcell_Config OF DIVcell IS
  FOR Structure
    FOR ALL : INV
      USE ENTITY work.INV(Behavior);
    END FOR;
    FOR ALL : AND2
      USE ENTITY work.AND2(Behavior);
    END FOR;
    FOR ALL : AND3
      USE ENTITY work.AND3(Behavior);
    END FOR;
    FOR ALL : AND4
      USE ENTITY work.AND4(Behavior);
    END FOR;
    FOR ALL : OR_3
      USE ENTITY work.OR_3(Behavior);
    END FOR;
    FOR ALL : OR5
      USE ENTITY work.OR5(Behavior);
    END FOR;
  END FOR;
END DIVcell_Config;