--==========================================================
-- Design units : DIVarray
--                (entity, architecture and configuration)
--
-- File name    : DIVarray.vhd
--
-- Purpose      : divider array 
--
-- Limitations  : k > m > 0
--
-- Library      : WORK
--
-- Dependencies : IEEE, ELEMpack, DIVpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    20.01.95       ESA standard
-- V1.0    hpe    03.04.95       comments
--=========================================================
--
-- The n-by-n bit restoring array devider requires n*n cells 
-- and the execution time is 2 times n to the power of two. 

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE work.ELEMpack.ALL;
USE work.DIVpack.ALL;

ENTITY DIVarray IS            -- N = Q*D + R
  GENERIC (M: Positive := 3;  -- bit length of divisor
           K: Positive := 6); -- bit length of dividend
  PORT (N: IN std_logic_vector(K-1 DOWNTO 0); -- dividend in
        D: IN std_logic_vector(M-1 DOWNTO 0); -- divisor in
        Q: INOUT std_logic_vector((K-M)-1 DOWNTO 0); -- quotient out
        R: OUT std_logic_vector(M-1 DOWNTO 0)); -- remainder out
END DIVarray;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF DIVARRAY IS

  SIGNAL CS2Out,Out2CS,CSdown: std_logic_vector ((K-M)-1 DOWNTO 0);
  
  SIGNAL DivIn,DivOut,BorrowIn,BorrowOut,RemIn,DifOut,
         SubIn,SubOut: std_logic_vector((M*(K-M))-1 DOWNTO 0); 

BEGIN

  Row    : FOR i IN 0 TO (K-M)-1 GENERATE
  Column : FOR j IN 0 TO M-1 GENERATE

  Init_Cell : DIVcell
    PORT MAP (DivIn => DivIn(M*i+j),
              Rem1 => RemIn(M*i+j),
              BorrowIn => BorrowIn(M*i+j),
              SubIn => SubIn(M*i+j),
              BorrowOut => BorrowOut(M*i+j),
              SubOut => SubOut(M*i+j),
              DivOut => DivOut(M*i+j),
              Dif => DifOut(M*i+j));
  
     Row_0 : IF i=0 GENERATE
       DivIn(j) <= D(j);
     END GENERATE;

     Row_i : IF i>0 GENERATE
       DivIn(M*i+j) <= DivOut(M*(i-1)+j);
     END GENERATE;

     Row_KM : IF i=K-M-1 GENERATE
       R(j) <= DifOut(M*(K-M-1)+j);
     END GENERATE;

     Column_0_0 : IF j=0 AND i=0 GENERATE
       BorrowIn(M*i) <= '0';
       RemIn(M*i) <= N(K-M-1);
       SubIn(M*i) <= SubOut(M*i+1);
     END GENERATE;

     Column_j_0 : IF j>0 AND j<M-1 AND i=0  GENERATE
       RemIn(M*i+j) <= N(K-M-1+j);
       BorrowIn(M*i+j) <= BorrowOut(M*i+j-1);
       SubIn(M*i+j) <= SubOut(M*i+j+1);
     END GENERATE;

     Column_M_0_1 : IF j=M-1 AND i=0 AND M=1 GENERATE
       RemIn(M*i+j) <= N(K-M-1+M-1);
       BorrowIn(M*i+j) <= '0';
       SubIn(M*i+j) <= Out2CS(i);       
     END GENERATE;

     Column_M_0_2 : IF j=M-1 AND i=0 AND M>1 GENERATE
       RemIn(M*i+j) <= N(K-M-1+M-1);
       BorrowIn(M*i+j) <= BorrowOut(M*i+j-1);
       SubIn(M*i+j) <= Out2CS(i);       
     END GENERATE;

     Column_0_i : IF j=0 AND i>0 GENERATE
       BorrowIn(M*i) <= '0';
       RemIn(M*i) <= N(K-M-1-i);
       SubIn(M*i) <= SubOut(M*i+1);
     END GENERATE;

     Column_j_i : IF j>0 AND j<M-1 AND i>0  GENERATE
       RemIn(M*i+j) <= DifOut(M*(i-1)+j-1);
       BorrowIn(M*i+j) <= BorrowOut(M*i+j-1);
       SubIn(M*i+j) <= SubOut(M*i+j+1);
     END GENERATE;

     Column_M_i_1 : IF j=M-1 AND i>0 AND M=1 GENERATE
       RemIn(M*i+j) <= N(K-M-1-i);
       BorrowIn(M*i+j) <= '0';
       SubIn(M*i+j) <= Out2CS(i);       
     END GENERATE;

     Column_M_i_2 : IF j=M-1 AND i>0 AND M>1 GENERATE
       RemIn(M*i+j) <= DifOut(M*(i-1)+j-1);
       BorrowIn(M*i+j) <= BorrowOut(M*i+j-1);
       SubIn(M*i+j) <= Out2CS(i);       
     END GENERATE;

    Output_Column : IF j=M-1 GENERATE

      Init_Output : DIVoutput
        PORT MAP (A => CS2Out(i),
                  B => CSdown(i),
                  Y => Q((K-M-1)-i),
                 nY => Out2CS(i));

      Output_0 : IF i=0 GENERATE
        CSdown(i) <= BorrowOut(M-1);
        CS2Out(i) <= N(K-1);
      END GENERATE;

      Output_j : IF i>0 GENERATE
        CSdown(i) <= BorrowOut(M*i+M-1);
        CS2Out(i) <= DifOut(M*i-1);
      END GENERATE;

    END GENERATE;

  END GENERATE;
  END GENERATE;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION DIVarray_Config OF DIVarray IS
  FOR Structure
    FOR Row
      FOR Column
        FOR Init_Cell : DIVcell
          USE ENTITY work.DIVcell(Structure);
        END FOR;
        FOR Output_Column
          FOR Init_Output : DIVoutput
            USE ENTITY work.DIVoutput(Structure);
          END FOR;
        END FOR;
      END FOR;
    END FOR;
  END FOR;
END DIVarray_Config;