--==========================================================
-- Design units : AssocMemPack
--                (entitiy, architecture and configuration)
--
-- File name    : AssocMemPack.vhd
--
-- Purpose      : Package for Associative Memory 
--
-- Limitations  : 
--
-- Library      : WORK
--
-- Dependencies : 
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95       new
-- V2.0    cjt    18.10.95       external stimuli
--===========================================================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;


PACKAGE AssocMempack IS

------------------------------------------------------------
-- Behavioral Description of an Associativ Memory ----------
------------------------------------------------------------

  COMPONENT AssocMemBehave
    GENERIC (M,N: Positive);
    PORT (Data,Mask: IN std_logic_vector(M-1 DOWNTO 0);
          Address: IN std_logic_vector(N-1 DOWNTO 0);
          Store,
          Search,
          Reset: IN std_logic;
          End1: OUT std_logic;
          Result: OUT std_logic_vector(M-1 DOWNTO 0));
  END COMPONENT;

------------------------------------------------------------
-- Behavioral Description of stimuli for Associativ Memory -
------------------------------------------------------------

  COMPONENT AssocMemStim
    GENERIC (M : Positive := 4;
             N : Positive := 3);
    PORT(WriteEnable : OUT std_logic;
         Data        : OUT std_logic_vector(M-1 DOWNTO 0);
         Mask        : OUT std_logic_vector(M-1 DOWNTO 0);
         Address     : OUT std_logic_vector(N-1 DOWNTO 0);
         Store       : OUT std_logic;
         SelectAdrMat: OUT std_logic;
         Reset       : OUT std_logic;
         Clock       : OUT std_logic);
  END COMPONENT;


------------------------------------------------------------
-- Structural Description of the Circuit -------------------
------------------------------------------------------------

  COMPONENT AssocMemCirc
    GENERIC (M,N: Positive);
    PORT (DataIn,MaskIn : IN std_logic_vector (M-1 DOWNTO 0);
          AddressIn     : IN std_logic_vector (N-1 DOWNTO 0);
          Store         : IN std_logic;
          SelectAdrMat  : IN std_logic;
          Clock         : IN std_logic;
          WriteEnable   : IN std_logic;
          Reset         : IN std_logic;
          End1          : OUT std_logic;
          DataOut       : OUT std_logic_vector(M-1 DOWNTO 0));
  END COMPONENT;

------------------------------------------------------------
-- The following components are needed for Structural ------
-- Description ---------------------------------------------
------------------------------------------------------------

  COMPONENT AssocMemArray
    GENERIC (M,N: Positive);
    PORT (WriteEnable   : IN std_logic;
          DataIn        : IN std_logic_vector(M-1 DOWNTO 0);
          Mask          : IN std_logic_vector(M-1 DOWNTO 0);
          Sel           : IN std_logic_vector(N-1 DOWNTO 0);
          DataOut       : OUT std_logic_vector(M-1 DOWNTO 0);
          Match         : OUT std_logic_vector(N-1 DOWNTO 0));
  END COMPONENT;

  COMPONENT AssocMemCell
    PORT (WriteEnable   : IN std_logic;
          DataIn        : IN std_logic;
          Mask          : IN std_logic;
          Sel           : IN std_logic;
          Match         : Out std_logic;
          DataOut       : Out std_logic);
  END COMPONENT;

  COMPONENT AssocMemCtrl
    PORT (Store         : IN std_logic;
          SelectAdrMat  : IN std_logic;
          WriteEnable   : IN std_logic;
          Reset         : IN std_logic;
          StoreRes      : OUT std_logic);
  END COMPONENT;

END AssocMempack;