--==========================================================
-- Design units : AssocMemArray
--                (entitiy, architecture and configuration)
--
-- File name    : AssocMemArray.vhd
--
-- Purpose      : Associative Memory 
--
-- Limitations  : None
--
-- Library      : WORK
--
-- Dependencies : AssocMemCirc, AssocMemCtrl, AssocMemCell
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-------------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    02.04.95       new
-- V2.0    cjt    18.10.95       ESA-Standard, Comments,
--                               Change of OR_x-Gates
--===========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.AssocMemPack.all;

ENTITY AssocMemArray IS
  GENERIC (M: Positive := 4;                              -- word length
           N: Positive := 4);                             -- memory width
  PORT (WriteEnable : IN std_logic;                       -- write enable
        DataIn      : IN std_logic_vector(M-1 DOWNTO 0);  -- data word in
        Mask        : IN std_logic_vector(M-1 DOWNTO 0);  -- mask word in
        Sel         : IN std_logic_vector(N-1 DOWNTO 0);  -- select word
        DataOut     : OUT std_logic_vector(M-1 DOWNTO 0); -- data word out
        Match       : OUT std_logic_vector(N-1 DOWNTO 0));-- match word out
END AssocMemArray;

--==========================ARCHITECTURE=====================

ARCHITECTURE Structure OF AssocMemArray IS
 
  -- Internal signals:

  SIGNAL Q_or,M_or,Q_collect,M_collect: std_logic_vector(0 to (M*N)-1);

BEGIN

  basic_case0: IF M=1 AND N=1 GENERATE

    u0 : AssocMemCell
         PORT MAP (WriteEnable,
                   DataIn(0),
                   Mask(0),
                   Sel(0),
                   Match(0),
                   DataOut(0));

  END GENERATE; -- end basic case 0

  basic_case1: IF M=1 AND N=2 GENERATE

    u1 : AssocMemCell
         PORT MAP (WriteEnable,
                   DataIn(0),
                   Mask(0),
                   Sel(0),
                   Match(0),
                   Q_or(0));

    u2 : AssocMemCell
         PORT MAP (WriteEnable,
                   DataIn(0),
                   Mask(0),
                   Sel(1),
                   Match(1),
                   Q_or(1));

    u3 : OR_2
         PORT MAP (Q_or(0),
                   Q_or(1),
                   DataOut(0));

  END GENERATE; -- end basic case 1

  basic_case2: IF M=2 AND N=1 GENERATE

    u4 : AssocMemCell
         PORT MAP (WriteEnable,
                   DataIn(0),
                   Mask(0),
                   Sel(0),
                   M_or(0),
                   DataOut(0));

    u5 : AssocMemCell
         PORT MAP (WriteEnable,
                   DataIn(1),
                   Mask(1),
                   Sel(0),
                   M_or(1),
                   DataOut(1));

    u6 : OR_2
         PORT MAP (M_or(0),
                   M_or(1),
                   Match(0));

  END GENERATE; -- end basic case 2

  general_case: IF M>=2 AND N>=2 GENERATE

    G0: FOR I IN 0 to M-1 GENERATE

      G1: FOR J IN 0 to N-1 GENERATE  

        memory_cells : AssocMemCell
          PORT MAP (WriteEnable,
                    DataIn(I),
                    Mask(I),
                    Sel(J),
                    M_or((I)*N+J),
                    Q_or((I)*N+J));

        wire_Q0 : IF J=1 AND J=N-1 GENERATE
          unit0 : OR_2
             PORT MAP (Q_or((I)*N),
                       Q_or((I)*N+1),
                       DataOut(I));
        END GENERATE;

        wire_Q1 : IF J=1 AND J<N-1 GENERATE
          unit1 : OR_2
            PORT MAP (Q_or((I)*N),
                      Q_or((I)*N+1),
                      Q_collect((I)*N+1));
        END GENERATE;

        wire_Q2 : IF J>1 AND J<N-1 GENERATE
          unit2 : OR_2
            PORT MAP (Q_or((I)*N+J),
                      Q_collect((I)*N+J-1),
                      Q_collect((I)*N+J));
        END GENERATE;

        wire_Q3 : IF J>1 AND J=N-1 GENERATE
          unit3 : OR_2
            PORT MAP (Q_or((I)*N+J),
                      Q_collect((I)*N+J-1),
                      DataOut(I));
        END GENERATE;

        wire_M0 : IF I=1 AND I=M-1 GENERATE
          unit4 : OR_2
            PORT MAP (M_or(J),
                      M_or(N+J),
                      Match(J));
        END GENERATE;

        wire_M1 : IF I=1 AND I<M-1 GENERATE
          unit5 : OR_2
            PORT MAP (M_or(J),
                      M_or(N+J),
                      M_collect(N+J));
        END GENERATE; 

        wire_M2 : IF I>1 AND I<M-1 GENERATE
          unit6 : OR_2
            PORT MAP (M_or((I)*N+J),
                      M_collect((I-1)*N+J),
                      M_collect((I)*N+J));
        END GENERATE;

        wire_M3 : IF I>1 AND I=M-1 GENERATE
          unit7 : OR_2
            PORT MAP (M_or((I)*N+J),
                      M_collect((I-1)*N+J),
                      Match(J));
        END GENERATE;


    END GENERATE; -- end index j

  END GENERATE; -- end index i

END GENERATE; -- end general case

END Structure;

--==========================CONFIGURATION====================

CONFIGURATION AssocMemArray_Config OF AssocMemArray IS

  FOR Structure

    FOR basic_case0

      FOR u0 : AssocMemCell
        USE ENTITY work.AssocMemCell(Structure);
      END FOR;

    END FOR; -- basic case 0

    FOR basic_case1

       FOR u1 : AssocMemCell
         USE ENTITY work.AssocMemCell(Structure);
       END FOR;

       FOR u2 : AssocMemCell
         USE ENTITY work.AssocMemCell(Structure);
       END FOR;

       FOR u3 : OR_2
         USE ENTITY work.or_2(Behavior);
       END FOR;

    END FOR; -- basic case 1

    FOR basic_case2

       FOR u4 : AssocMemCell
         USE ENTITY work.AssocMemCell(Structure);
       END FOR;

       FOR u5 : AssocMemCell
         USE ENTITY work.AssocMemCell(Structure);
       END FOR;

       FOR u6 : OR_2
         USE ENTITY work.or_2(Behavior);
       END FOR;

    END FOR; -- basic case 2

    FOR general_case

      FOR g0

        FOR g1

          FOR ALL : AssocMemCell
            USE ENTITY work.AssocMemCell(Structure);
          END FOR;

          FOR wire_Q0

            FOR unit0 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_Q1

            FOR unit1 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_Q2

            FOR unit2 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_Q3

            FOR unit3 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_M0

            FOR unit4 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_M1

            FOR unit5 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_M2

            FOR unit6 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

          FOR wire_M3

            FOR unit7 : OR_2
              USE ENTITY work.or_2(Behavior);
            END FOR;

          END FOR;

        END FOR; -- g1

      END FOR; -- g0

    END FOR; -- general case

  END FOR; -- Structure

END AssocMemArray_Config;