--==========================================================
-- Design units : ArbiterTest
--
-- File name    : ArbiterTest.vhd
--
-- Purpose      : Testbench for arbiter
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    10.04.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.ArbiterPack.all;

ENTITY ArbiterTest IS
END ArbiterTest;


--============================ARCHITECTURE==================

ARCHITECTURE Structure OF ArbiterTest IS

CONSTANT N : Positive := 4;

SIGNAL Request,Acknowledge: std_logic_vector(N-1 DOWNTO 0);
SIGNAL Clk,reset: std_logic;
SIGNAL Check: std_logic_vector(N DOWNTO 0);

BEGIN

MUT: Arbiter_Struc
  GENERIC MAP(N)
  PORT MAP(Request,Clk,reset,Acknowledge);

STIM: Arbiter_Stim
  GENERIC MAP(N)
  PORT MAP(Clk,reset,Request);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION ArbiterTestConfig OF ArbiterTest IS

FOR Structure

  FOR MUT: Arbiter_Struc
    USE ENTITY work.arbiter_struc(Structure);
  END FOR;

  FOR STIM: Arbiter_Stim
    USE ENTITY work.arbiter_stim(Behavior);
  END FOR;

END FOR;

END ArbiterTestConfig;