--========================================================== -- Design units : Arbiter_Struc(Entity,Architecture,Configuration) -- -- File name : ArbiterStruc.vhd -- -- Purpose : Synchronous arbiter for n hosts -- -- Limitations : - -- -- Library : IEEE -- -- Dependencies : ELEMpack -- -- Author : Claus-Juergen Thomas, REFT -- -- Simulator : Synopsys V3.2a on SUN SPARCstation 10 -- ----------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- v1.0 cjt 10.04.96 new --========================================================= LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.ELEMpack.all; USE work.ArbiterPack.all; ENTITY Arbiter_Struc IS GENERIC(N : POSITIVE := 4); PORT(req_in : IN std_logic_vector(N-1 DOWNTO 0); clk : IN std_logic; reset : IN std_logic; -- asynchronous reset on active low ack_out: OUT std_logic_vector(N-1 DOWNTO 0)); END Arbiter_Struc; --============================ARCHITECTURE================== ARCHITECTURE Structure OF Arbiter_Struc IS SIGNAL token,override,grant: std_logic_vector(N DOWNTO 0); SIGNAL zero: std_logic := '0'; BEGIN first: Arbiter_Cell_1 PORT MAP(req_in (0), grant(0), token(0), override(1), clk, reset, ack_out(0), grant(1), token(1), override(0)); i_loop: FOR i IN 1 TO N-1 GENERATE Cell: Arbiter_Cell_2_plus PORT MAP(req_in (i), grant(i), token(i), override(i+1), clk, reset, ack_out(i), grant(i+1), token(i+1), override(i)); END GENERATE; token(0) <= token(N); override(N) <= zero; Gate1: INV PORT MAP(override(0), grant(0)); END Structure; --============================CONFIGURATION================= CONFIGURATION Arbiter_Struc_Config OF Arbiter_Struc IS FOR Structure FOR first: Arbiter_Cell_1 USE ENTITY work.arbiter_cell_1(Structure); END FOR; FOR i_loop FOR Cell: Arbiter_Cell_2_plus USE ENTITY work.arbiter_cell_2_plus(Structure); END FOR; END FOR; FOR Gate1: INV USE ENTITY work.inv(Behavior); END FOR; END FOR; END Arbiter_Struc_Config;