--==========================================================
-- Design units : Arbiter_Package
--
-- File name    : ArbiterPack.vhd
--
-- Purpose      : declares elements for simulation of arbiter
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    10.04.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;

PACKAGE ArbiterPack IS

COMPONENT Arbiter_Cell_1
  PORT(req_in      : IN std_logic;
       grant_in    : IN std_logic;
       token_in    : IN std_logic;
       override_in : IN std_logic;
       clk         : IN std_logic;
       reset       : IN std_logic;
       ack_out     : OUT std_logic;
       grant_out   : OUT std_logic;
       token_out   : OUT std_logic;
       override_out: OUT std_logic);
END COMPONENT;

COMPONENT Arbiter_Cell_2_plus
  PORT(req_in      : IN std_logic;
       grant_in    : IN std_logic;
       token_in    : IN std_logic;
       override_in : IN std_logic;
       clk         : IN std_logic;
       reset       : IN std_logic;
       ack_out     : OUT std_logic;
       grant_out   : OUT std_logic;
       token_out   : OUT std_logic;
       override_out: OUT std_logic);
END COMPONENT;

COMPONENT Arbiter_Struc
  GENERIC(N : POSITIVE := 4);
  PORT(req_in : IN std_logic_vector(N-1 DOWNTO 0);
       clk    : IN std_logic;
       reset  : IN std_logic;
       ack_out: OUT std_logic_vector(N-1 DOWNTO 0));
END COMPONENT;

COMPONENT Arbiter_Stim
  GENERIC(N : POSITIVE := 4);
  PORT(clk    : OUT std_logic;
       reset  : OUT std_logic;
       request: OUT std_logic_vector(N-1 DOWNTO 0));
END COMPONENT;

END ArbiterPack;