--==========================================================
-- Design units : Arbiter_Cell_1(Entity,Architecture,Configuration)
--
-- File name    : ArbiterCell1.vhd
--
-- Purpose      : provides arbitration for one host, generates token
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.2a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
--  v1.0   cjt    10.04.96       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;

ENTITY Arbiter_Cell_1 IS
PORT(req_in      : IN std_logic;
     grant_in    : IN std_logic;
     token_in    : IN std_logic;
     override_in : IN std_logic;
     clk         : IN std_logic;
     reset       : IN std_logic;    -- asynchronous reset on active low
     ack_out     : OUT std_logic;
     grant_out   : OUT std_logic;
     token_out   : OUT std_logic;
     override_out: OUT std_logic);
END Arbiter_Cell_1;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Arbiter_Cell_1 IS

  SIGNAL token,wt,int1,int2,int3,int4,int5,int6,int7: std_logic := '0';

  BEGIN

    Gate1: OR_2
      PORT MAP(token,
               wt,
               int1);

    Gate2: AND2
      PORT MAP(int1,
               req_in,
               int2);

    Gate3: AND2
      PORT MAP(wt,
               token,
               int3);

    Gate4: OR_2
      PORT MAP(int3,
               override_in,
               override_out);

    Gate5: INV
      PORT MAP(req_in,
               int4);

    Gate6: AND2
      PORT MAP(int4,
               grant_in,
               grant_out);

    Gate7: OR_2
      PORT MAP(int3,
               grant_in,
               int5);

    Gate8: AND2
      PORT MAP(req_in,
               int5,
               ack_out);

    Gate9: INV
      PORT MAP(token_in,
               int6);


    Reg1: DFFsr
      PORT MAP(int6,
               clk,
               reset,
               clk,
               int7);

    Gate10: INV
      PORT MAP(int7,
               token);

    Reg2: DFFsr
      PORT MAP(int2,
               clk,
               reset,
               clk,
               wt);

    token_out <= token;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Arbiter_Cell_Config OF Arbiter_Cell_1 IS

  FOR Structure

    FOR all: OR_2
      USE ENTITY work.or_2(Behavior);
    END FOR;

    FOR all: AND2
      USE ENTITY work.and2(Behavior);
    END FOR;

    FOR all: INV
      USE ENTITY work.inv(Behavior);
    END FOR;

    FOR all : DFFsr
      USE ENTITY work.DFFsr(Behavior);
    END FOR;

  END FOR;

END Arbiter_Cell_Config;