--==========================================================
-- Design units : CarryLookaheadPackage
--
-- File name    : CarryLookaheadPack.vhd
--
-- Purpose      : required elemets for CLA_N-Bit_Adder
--
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : ELMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- v1.0    cjt    19.12.95       new
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

PACKAGE CarryLookaheadPackage IS

COMPONENT Bit_Add_G_P
  PORT(A_In  : IN std_logic;      -- First summand
       B_In  : IN std_logic;      -- Second summand
       C_In  : IN std_logic;      -- Carry IN
       S_Out : OUT std_logic;     -- Sum OUT
       G_Out : OUT std_logic;     -- Carry GENERATE OUT
       P_Out : OUT std_logic);    -- Carry propagate OUT
END COMPONENT;

COMPONENT Carry_Generator
  PORT(gen          : IN std_logic_vector(0 to 3);    -- Generate input
       propagate    : IN std_logic_vector(0 to 3);    -- Propagate input
       CarryIn      : IN std_logic;                   -- Carry input
       CarryOut     : OUT std_logic_vector(0 to 2);   -- Carry output
       B_Carry      : OUT std_logic;                  -- Block carry output
       B_Propagate  : OUT std_logic;                  -- Block carry propagate output
       B_Generate   : OUT std_logic);                 -- Block carry GENERATE output
END COMPONENT;

COMPONENT Four_bit_Adder
  PORT(A_In  : IN std_logic_vector(0 to 3);   -- First summand
       B_In  : IN std_logic_vector(0 to 3);   -- Second summand
       C_In  : IN std_logic;                  -- Carry IN
       S_Out : OUT std_logic_vector(0 to 3);  -- Sum OUT
       BP_Out: OUT std_logic;                 -- Block carry propagate OUT
       BG_Out: OUT std_logic;                 -- Block carry GENERATE OUT
       BC_Out: OUT std_logic);                -- Block carry OUT
END COMPONENT;

COMPONENT Carry_Lookahead_Adder
  GENERIC(M: POSITIVE := 8);
  PORT(DataIn_A: IN  std_logic_vector(M-1 DOWNTO 0);
       DataIn_B: IN  std_logic_vector(M-1 DOWNTO 0);
       CarryIn : IN  std_logic;
       DataOut : OUT std_logic_vector(M-1 DOWNTO 0);
       CarryOut: OUT std_logic);
END COMPONENT;

END CarryLookaheadPackage;